Force SPARC/CPCI-520G, Technical Reference Manual

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I/O-52x(G) Installation Front Panel and Connectors
SPARC/CPCI-52x(G) Page 59
Installation Guide. For the J5 connector pinout see figure 22 “CompactP-
CI J5 connector pinout” on page 60.
5.4.2 PMC Slots
The I/O-52x(G) provides 2 PMC slots compliant with IEEE P1386
("Draft Standard Physical and Environmental Layers for PCI Mezzanine
Cards: PMC"). The PCI bus, a high speed local bus, connects different
high speed I/O cards with the SPARC/CPCI-52x(G). Both PMC slots
support 32-bit data bus width with a maximum frequency of 33 MHz.
PMC Voltage
Keys The PCI bus uses a 5V voltage to signal bus levels. The voltage keys pre-
vent 3.3V PMC cards from being plugged into the PMC slots.
Connector
Configuration The 32-bit PCI bus requires 2 PMC connectors. The 3rd PMC connector
(PNx4) connects additional user I/O signals of PMC slot 1 and PMC
slot 2 to the CompactPCI J4 connector.
PMC slot 1
connectors • for the PCI bus: PN11 and PN12
• for 64 user I/O signals: PN14
PMC slot 2
connectors • for the PCI bus: PN21 and PN22
• for 32 user I/O signals: PN24
5.4.3 CompactPCI Backplane Connector Pinout
J1 and J2 The J1 and J2 connectors implement the CompactPCI 64-bit connector
pinout as specified by the CompactPCI specification. Therefore, this
manual only documents the pinout of the J4 and J5 connector.
J4 and J5 Besides the CompactPCI specific pinout the following interfaces are
available on the CompactPCI J4 and J5 connector.
• SCSI #2, MII #2
• User I/O pins for PMC #1 and #2 (
PMC #1, PMC #2
)