Force SPARC/CPCI-520G, Technical Reference Manual

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Hardware Description Processor – UltraSPARC-IIi
SPARC/CPCI-52x(G) Page 69
6.1.1 Physical Memory Map
Table 29 UltraSPARC-IIi physical address map (41-bit physical addresses)
Address range in
PA<40:0>
Size
Addressed
interface Access
type
000.0000.0000
16
…000.3FFF.FFFF
16
1 GByte Main memory cacheable
000.4000.0000
16
…1FF.FFFF.FFFF
16
reserved undefined cacheable
000.0000.0000
16
…1FB.FFFF.FFFF
16
reserved undefined noncacheable
1FC.0000.0000
16
…1FD.FFFF.FFFF
16
8 GByte UPA64S noncacheable
1FE.0000.0000
16
…1FF.FFFF.FFFF
16
8 GByte PCI noncacheable
Table 30 UltraSPARC-IIi internal CSR space (16 MByte)
Address range in
PA<40:0>
Size Description/owner
1FE.0000.0000
16
…1FE.0000.01FF
16
512 Byte PBM (PCI bus module)
1FE.0000.0200
16
…1FE.0000.03FF
16
512 Byte IOM (IO memory management
unit)
1FE.0000.0400
16
…1FE.0000.1FFF
16
7 KByte PIE (PCI interrupt)
1FE.0000.2000
16
…1FE.0000.5FFF
16
16 KByte PBM
1FE.0000.6000
16
…1FE.0000.9FFF
16
12 KByte PIE
1FE.0000.A000
16
…1FE.0000.A7FF
16
2 KByte IOM
1FE.0000.A800
16
…1FE.0000.EFFF
16
22 KByte PIE
1FE.0000.F000
16
…1FE.00FF.F018
16
23 MByte MCU (memory control unit)
1FE.00FF.F020
16
8 Byte PIE
1FE.00FF.F028
16
…1FE.00FF.FFFF
16
4 KByte MCU