Ethernet and EBus2 Devices – PCIO
Hardware Description
Page 96
SPARC/CPCI-52x(G)
See
I2C_SDAO
for information how to write data to I
2
C Bus slaves. See
I2C_SDAI
for information how to read data from I
2
C Bus slaves.
I2C_SDAO
(r/w)
I2C_SDAO
is used to force low (
0
) or high (
1
) level on the I
2
C Bus data
line.
Note: Whenever data is read from another I
2
C Bus participant,
I2C_SDAO
must be set to
1
, otherwise data is corrupted.
= 0
Low level (
0
) is forced on the data line.
= 1
High level (
1
) is forced on the data line.
Note: Since the I2C_SDAO is realized as an open collector output
onto the I
2
C Bus data line, it is necessary to be aware of the typical
RC-time constant. This time constant is 5 usec. It is important that
the read-out of the data line via I2C_SDAI, which immediately
follows the setting of the SDA data line to the high level
1
, strictly
respects the 5 usec time constant before executing the read-out.
Otherwise the data will be read incorrectly on I2C_SDAI.
I2C_SCL
(r/w)
I2C_SCL
is used to control the state of the clock line of the I
2
C bus.
= 0
Low level (
0
) is forced on the data line.
= 1
High level (
1
) is forced on the data line.
I2C_SDAI
(ro)
I2C_SDAI
is used to read data from the I
2
C Bus data line. However, to
do so
I2C_SDAO
must be set to
1
, otherwise data is corrupted.
•
If
I2C_SDAO
is set (
1
), the state of
I2C_SDAI
indicates the state of
the data line of the I
2
C bus.
•
If
I2C_SDAO
is cleared (
0
), low level (
0
) is forced on the data line
of the I
2
C bus and
I2C_SDAI
is cleared, too.
Table 55
I
2
C Bus Control and Status Register
F160.0003
16
Bit
7
6
5
4
3
2
1
0
Value
1
1
1
1
reser
ved
I2C_
SDAO
I2C_
SCL
I2C_
SDAI
Summary of Contents for SPARC/CPCI-520G
Page 6: ...Contents Page iv SPARC CPCI 52x G...
Page 14: ...Using This Manual Page xii SPARC CPCI 52x G...
Page 18: ...Page 4 SPARC CPCI 52x G...
Page 20: ...Introduction Page 6 SPARC CPCI 52x G...
Page 24: ...Ordering Information Introduction Page 10 SPARC CPCI 52x G...
Page 58: ...OpenBoot Firmware Base 520 G Installation Page 44 SPARC CPCI 52x G...
Page 66: ...OpenBoot Firmware Base 520 G Installation Page 52 SPARC CPCI 52x G...
Page 102: ...Ethernet and EBus2 Devices PCIO Hardware Description Page 88 SPARC CPCI 52x G...
Page 114: ...PMC Slots with Busmode Support Hardware Description Page 100 SPARC CPCI 52x G...
Page 134: ......