Force SPARC/CPCI-520G, Technical Reference Manual

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Hardware Description Ethernet and EBus2 Devices – PCIO
SPARC/CPCI-52x(G) Page 83
6.3.6 RTC/NVRAM – M48T58
The Base-520(G) provides a RTC/NVRAM – M48T58 at PCI bus base
address
F100.000016
on the EBus2.
Device features • 8 KByte ultra low power CMOS SRAM
• Byte-wide accessible real-time clock and power-fail control circuit
for automatic power-fail chip deselect and write protection
• Long-life lithium carbon monofluoride battery
• Year-2000 compliant RTC with own crystal
Table 40 Address map of the RTC/NVRAM
Address offset
range
Access
0000
16
…
1FF7
16
NVRAM with 8 KByte minus 8 bytes capacity
1FF8
16
…
1FFF
16
RTC registers with clock information in 24-hour
BCD format: year, month, date, day, hour, minute,
second