Eaton XN300, Manual

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31 Counter module XN-322-1CNT-8DIO
31.6 Memory layout
266
XN300 slice modules 06/16 MN050002 EN www.eaton.com
0x30F1 4 Pause time, measured by counting internal clock signals in this 32-bit counter register.
The register contains the number of pulses, from an internal time reference, counted between the last two counter value
increments (rising edges on signal A). The register value with the counted pulses is refreshed with a rising edge on A or
when the maximum value is reached. Accordingly, this register makes it possible to represent count pulses per time unit for
the frequency or speed measurement. The direction (sign) is determined based on the evaluation of the signal sequence
when in AB quadrature mode.
0x30F2 2 Counter value (16-bite incremental encoder counter value)
The counter resolves edges into numbers of pulses and directions. X1, X2 and X4 encoding are available.
0x30F3 2 Stored counter value (stored 16-bit incremental encoder counter value)
This register contains the counter value stored by a latch pulse. The input that triggers this action must be configured accord-
ingly.
0x30F4 1 Incremental encoder status register Bit 0-3 reserved
Bit 4 Zero position
Bit 5 reserved
Bit 6
(State +24V X4) 24 VDC OK on supply to outputs
Bit 7
(State +24V X1/X2) 24 VDC OK on supply to incremental encoder
0x40F2
(WRITE) 4 Max. waiting time value (count range for the waiting time register (max. 31-bit))
This register uses the register width to define the maximum value for the waiting time. When the maximum value is reached,
a motor stop is identified, for example.
0x40F3 1 Cycle prescaler for determining the waiting time
Prescaler periods = Cycle [Hz] * Measuring time [sec]
0x40F4
(READ) 1 Pulse frequency (System Clock)
Pulse frequency in MHz
0x40F5 2 Counter value as acyclical access (16-bit incremental encoder counter value)
0x40F6 1 Incremental encoder configuration
register Bit 0 …1 reserved
Bit 2 Inverted logic for R zero-position evaluation
Bit 3 Inverted logic for B phase evaluation
Bit 4 …5 Bit
5
Bit
4 Signal analysis
0 0 off
0 1 single encoding
1 0 double encoding
1 1 four sample encoding
Bit 6 … 7 reserved
CAN object Size
(byte) Description