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The time T
H
is reset if the status at input Trg is reset to 0 before this time has expired.
The time T
L
is triggered with the 1 to 0 transition at the output.
If the status at input Trg remains 0 at least for the duration of a configured time T
L
, the output
is reset to 0 upon expiration of this time (output is off delayed to the input signal).
The time T
L
is reset if the status at input Trg is returns to 1 before this time has expired.
4
4
4
4.4.4
.4.4
.4.4
.4.4 Retentive
Retentive
Retentive
Retentive on-delay
on-delay
on-delay
on-delay
Short
Short
Short
Short description
description
description
description
A one-shot at the input triggers a configurable time. The output is set upon expiration of this
time.
Connection
Connection
Connection
Connection
Description
Description
Description
Description
Input
Trg
Trg
Trg
Trg
Trigger the on delay time via the Trg (Trigger) input.
Input
R
R
R
R
Reset the time on delay time and reset the output to 0 via
input R (Reset).
Reset takes priority over Trg.
Parameter
T
T
T
T
is the on delay time for the output (output signal transition
0 to 1).
Retentivity
Retentivity
Retentivity
Retentivity
on = the status is retentive in memory.
Output
Q
Q
Q
Q
Q is switched on upon expiration of the time T.
Parameter
Parameter
Parameter
Parameter
The time in parameter T can be provided by the value of another already-programmed
function:
Analog comparator: Ax – Ay
Analog trigger: Ax
Analog amplifier: Ax
Analog multiplexer: AQ
Analog ramp: AQ
Analog math: AQ
PI controller:AQ
Data latching relay: AQ
Up/Down counter: Cnt
The value of
"T"
can be set/modified in parameter mode. For information about how to
modify, refer to chapter 5.2.2 please.
Timing
Timing
Timing
Timing diagram
diagram
diagram
diagram
Summary of Contents for xLogic
Page 1: ......
Page 2: ......
Page 102: ...100 100 100 100 B B B B Blocks Blocks Blocks Blocks...
Page 105: ...103 103 103 103 G G G G M M M M status status status status...
Page 106: ...104 104 104 104 H H H H AM AM AM AM value value value value...
Page 164: ...162 162 162 162 If the Memory Read block had been triggered the Q1 of ELC 12 CPU will be set 1...
Page 204: ...202 202 202 202 Step Step Step Step 6 6 6 6 Moving Moving Moving Moving...
Page 226: ...224 224 224 224...