Control Conditioning Circuit
The CPU generates a 400 µs low pulse rate train at a 160 Hz rate on signal DISP PHASE. Half of U34 takes
DISP PHASE as an input and creates DISP POL as an 80 Hz 50% duty cycle square wave. A CPU reset
initializes DISP POL low when any CPU reset occurs so the software knows the initial state. The other half of
U34 is used to synchronize the rising edge of the DISP DL iwht the rising edge of DISP POL. The CPU brings
DISP LATCH signal high before the rising edge of DISP PHASE; this allows the high to be clocked out to DISP
DL on the rising edge of DISP PHASE. About 100 µs after the rising edge of DISP PHASE, the CPU brings
IDSP LATCH low, asynchronously resetting DISP DL low.
Display Driver Control Circuits
U19 and U20 are the display segment driver chips. Each chip has 32 high-voltage outputs and a display common
marked BP (backplane). The display data are input to U19 and U20 by the CPU via a serial shift register input.
U19 and U20 are daisy-chained together forming a 64-bit serial shift register. Display data are loaded and
shifted down via the DISP DATA and DISP CLK signals When all 64 bits of the shift register are loaded, a high
pulse on DISP DL updates the display, all 64 bits at the same time. The display is clocked with an 80 Hz 50%
duty cycle waveform by signal DISP POL. The display cannot be driven by DC voltages or display damage will
result. Display segments are illuminated by creating a 180-degree phase shift between the segment pin and the
BP common pin. Segments are left dark by making the waveform on the segment pin be in phase with the BP
pin. The display has an electroluminescent (EL) backlight, and is driven the same as the display segments.
Connectors JP2, JP3, and JP5 connect the display and EL backlight to the drive electronics.
High Voltage Control Circuit
The cold switch circuit performs two basic functions: (1) it allows the CPU to enable and disable the display high
voltage VDISP, and (2) it slows the edge slew rate of the segment drivers as it switches the high voltage. When
the signal DISP PHASE is low, Q14 is disabled, pulling VDISP low. Whenever the CPU is powered on, DISP
PHASE is tristated. The base emitter junction of Q12 pulls DISP PHASE low, disabling the high voltage. This
assures that the high voltage is only enabled to the display when controlled by the CPU.
The Taliq display is similar to an LCD in that the load of a segment is mainly capacitive. A cold switch circuit
provides a current-limited 70 V to VDISP. R93, R95, Q21 and Q14 do the on/off switching and current limiting.
As the driver chips' output waveforms and DISP PHASE change states, the capacitive output current is
integrated into the display capacitive loads, causing a highly linear rising and falling voltage ramp on VDISP.
Because the high voltage to the drive chips (VDISP) is ramped, the outputs of the driver chips U19 and U20 are
also ramped at the same controlled rate. This design is used to reduce current spikes on the 70 V power supply,
and, in addition, reduces the EMI generated by the display due to the lower slew rates of the high voltage
switching signals.
Standard User Controls
The standard user controls consist of two momentary push-button switches (measure and check-battery). The
measure button is an elastomeric contact switch, and the check-battery button is a mechanical momentary switch.
The CPU input lines BAT BTN an GO BTN are normally pulled to the high state by R71 and R78. Whenever a
button is depressed, the CPU input line is pulled low through R74 and R80. The switch contacts are debounced
with C64 and C66. L11, L12, C126, and C123 provide a current path for ESD protection.
In addition to being read by the CPU, the measure button also activates the power supply via the power control
circuit. Note that the measure button has circuitry on both the main PCB as well as the auxiliary PCB.
12-18