Atmel FPSLIC AT94KAL Series Manual Download

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168

AT94KAL Series FPSLIC

Rev. 1138G–FPSLI–11/03

AC Timing Characteristics – 3.3V Operation

Delays are based on fixed loads and are described in the notes.
Maximum times based on worst case: V

= 3.0V, temperature = 70

Minimum times based on best case: V

= 3.6V, temperature = 0

Maximum delays are the average of t

PDLH

and t

PDHL

Clocks and Reset Input buffers are measured from a V

of 1.5V at the input pad to the internal V

of 50% of V

Maximum times for clock input buffers and internal drivers are measured for rising edge delays only.

Cell Function

Parameter

Path

Device

-25

Units

Notes

Global Clocks and Set/Reset

GCK Input Buffer

(Maximum)

pad -> clock

AT94K05
AT94K10
AT94K40

1.2
1.5
1.9

Rising Edge Clock

FCK Input Buffer

(Maximum)

pad -> clock

AT94K05
AT94K10
AT94K40

0.7
0.8
0.9

Rising Edge Clock

Clock Column Driver

(Maximum)

clock -> colclk

AT94K05
AT94K10
AT94K40

1.3
1.8
2.5

Rising Edge Clock

Clock Sector Driver

(Maximum)

colclk -> secclk

AT94K05
AT94K10
AT94K40

1.0
1.0
1.0

Rising Edge Clock

GSRN Input Buffer

(Maximum)

colclk -> secclk

AT94K05
AT94K10
AT94K40

5.4

8.2

–

Global Clock to Output

(Maximum)

clock pad -> out

AT94K05
AT94K10
AT94K40

12.6
13.4
14.5

ns
ns

Rising Edge Clock

Fully Loaded Clock Tree

Rising Edge DFF

20 mA Output Buffer

50 pf Pin Load

Fast Clock to Output

(Maximum)

clock pad -> out

AT94K05
AT94K10
AT94K40

12.1
12.7
13.5

Rising Edge Clock

Fully Loaded Clock Tree

Rising Edge DFF

20 mA Output Buffer

50 pf Pin Load

Summary of Contents for FPSLIC AT94KAL Series

Page 1: ...nsive On chip Debug Support Limited Boundary scan Capabilities According to the JTAG Standard AVR Ports AVR Fixed Peripherals Industry standard 2 wire Serial Interface Two Programmable Serial UARTs Two 8 bit Timer Counters with Separate Prescaler and PWM One 16 bit Timer Counter with Separate Prescaler Compare Capture Modes and Dual 8 9 or 10 bit PWM Support for FPGA Custom Peripherals AVR Periphe...

Page 2: ... no ICE support and 4201J with ICE support see Figure 1 2 FPSLIC devices should be laid out during PCB design to support a split power supply Please refer to the Designing in Split Power Supply Support for AT94KAL and AT94SAL Devices application note available on the Atmel web site at http www atmel com atmel acrobat doc2308 pdf Table 1 The AT94K Series Characteristics Device AT94K05AL AT94K10AL A...

Page 3: ...gure 2 AT94K Series Architecture AT94K40AL 25DQC 0H1230 4201J Date Code J indicates JTAG ICE support 5 40K Gates FPGA Up to 16K x 8 Data SRAM Up to 16K x 16 Program SRAM Memory PROGRAMMABLE I O with Multiply Two 8 bit Timer Counters 16 Prog I O Lines I O I O I O 2 wire Serial Unit Up to 16 Interrupt Lines Up to 16 Addr Decoder 4 Interrupt Lines JTAG ICE ...

Page 4: ...ster than con ventional CISC microcontrollers at the same clock frequency The AVR executes out of on chip SRAM Both the FPGA configuration SRAM and the AVR instruction code SRAM can be automatically loaded at system power up using Atmel s In System Programmable ISP AT17 Series EEPROM Configuration Memories or ATFS FPSLIC Support Devices State of the art FPSLIC design tools System Designer were dev...

Page 5: ...omatic Component Generators The AT40K is capable of implementing user defined automatically generated macros speed and functionality are unaffected by the macro orientation or density of the target device This enables the fastest most predictable and efficient FPGA design approach and minimizes design risk by reusing already proven functions The Automatic Component Generators work seamlessly with ...

Page 6: ...ans four cells and connects to consecutive repeaters Each express bus segment spans eight cells and bypasses a repeater Repeaters regenerate signals and can connect any bus to any other bus all pathways are legal on the same plane Although not shown a local bus can bypass a repeater via a programmable pass gate allowing long on chip tri state buses to be created Local local turns are implemented t...

Page 7: ...7 AT94KAL Series FPSLIC Rev 1138G FPSLI 11 03 Figure 4 Busing Plane One of Five Local local or Express express Turn Point AT40K Core Cell Row Repeater Column ...

Page 8: ...ammable muxes and pass gates are legal Vn is connected to the vertical local bus in plane n Hn is connected to the hor izontal local bus in plane n A local local turn in plane n is achieved by turning on the two pass gates connected to Vn and Hn Up to five simultaneous local local turns are possible The logic cell can be configured in several modes The logic cell flexibility makes the FPGA archite...

Page 9: ... SET CLOCK FB X Diagonal Direct Connect or Bus Y Orthogonal Direct Connect or Bus W Bus Connection Z Bus Connection FB Internal Feedback 1 0 Z D Q 1 NW NE SE SW 1 1 1 0 X W Y X Z W Y 1 N E S W 8 X 1 LUT 8 X 1 LUT X Y NW NE SE SW N E S W V1 H1 V2 H2 V3 H3 V4 H4 V5 H5 1 OEH OEV L ...

Page 10: ...ctor rows A four bit Output Data bus connects to four horizontal local buses Plane 2 distributed over four sector rows A five bit Input address bus connects to five verti cal express buses in the same sector column column 3 A five bit Output address bus connects to five vertical express buses in the same column WAddr Write Address and RAddr Read Address alternate positions in horizontally aligned ...

Page 11: ...es are transparent when Load is logic 1 data flows through when Load is logic 0 data is latched Each bit in the 32 x 4 dual port RAM is also a transparent latch The front end latch and the memory latch together and form an edge triggered flip flop When a bit nibble is Write addressed and LOAD is logic 1 and WE is logic 0 DATA flows through the bit When a nibble is not Write addressed or LOAD is lo...

Page 12: ...dual port the switches on READ ADDR and DATA OUT would be on The other two would be off The reverse is true for single port Write Data Data Read 1 1 Write RAM Clear DATA 1 CLOCK Load 5 READ ADDR WRITE ADDR WE DATA IN Load Latch Load Latch Load Latch Clear 32 x 4 Dual port RAM OE 4 4 5 ...

Page 13: ...ut 4 Dout 5 Dout 6 Dout 7 Din Dout WE OE RAddr WAddr Din Dout Din Dout WE OE Din Dout WAddr RAddr WE OE RAddr WAddr WE OE WAddr RAddr Din Dout WAddr RAddr WE OE Din Dout WE OE RAddr WAddr Din Dout WAddr RAddr WE OE Din Dout WE OE RAddr WAddr 2 to 4 Decoder Local Buses Express Buses Dedicated Connections Read Address Din 0 Din 1 Din 2 Din 3 Din 4 Din 5 Din 6 Din 7 Write Address WE Dout 0 Dout 1 Dou...

Page 14: ...verted The register in each cell is triggered on a rising clock edge On power up constant 0 is provided to each register s clock pins A dedicated Global Set Reset bus see Figure 9 can be driven by any USER I O pad except those used for clocking Global or Fast An internal signal can be placed on the Global Set Reset bus by routing that signal to the pad programmed as the Glo bal Set Reset input Glo...

Page 15: ...AL clock input will be off If the TOSC clock input is used as an FPGA clock GCK6 in Idle mode it will still be running in Power save mode but will be off in Power down mode If the Watchdog Timer is used as an FPGA clock GCK6 and was enabled in the AVR it will be running in all sleep modes Table 3 Clock Activity in Various Modes Mode Clock Source GCK5 GCK6 Idle XTAL Active Active TOSC Not Available...

Page 16: ... Rev 1138G FPSLI 11 03 Figure 12 Clocking for One Column of Cells Note 1 Two on left edge column of the embedded FPGA array only Global Clock Line Buried Express Bus Plane 4 Half Length at Edge GCK1 GCK8 Repeater 1 1 1 1 FCK 1 ...

Page 17: ...urces Table 4 shows which buses are used in a dual function mode and which bus plane is used The FPGA software tools are designed to automatically accommodate dual function buses in an efficient manner Each Cell has a Programmable Set or Reset Global Set Reset Line Buried Repeater Express Bus Plane 5 Half Length at Edge Any User I O can Drive Global Set Reset Line 1 1 1 1 ...

Page 18: ...Write Enable Express 1 Vertical Bus full length at array edge bus in first column to left of RAM block FreeRAM Address Express 1 5 Vertical Buses full length at array edge buses in second column to left of RAM block FreeRAM Data In Local 1 Horizontal FreeRAM Data Out Local 2 Horizontal Clocking Express 4 Vertical Bus full length at array edge Set Reset Express 5 Vertical Bus full length at array e...

Page 19: ...6 Primary and Secondary I Os CELL 0 1 DRIVE TRI STATE 0 1 TTL CMOS SCHMITT DELAY PULL DOWN PULL UP GND VCC PAD CELL CLK RST RST CLK cell cell cell cell cell cell cell cell cell cell cell cell p p p p p p p p p p p p s s s s s s s s p s s secondary I O p primary I O cell p s cell p ...

Page 20: ...E TTL CMOS SCHMITT DELAY PULL DOWN PULL UP GND VCC PAD DRIVE TRI STATE TTL CMOS SCHMITT DELAY PULL DOWN PULL UP GND VCC PAD 0 1 0 1 0 1 0 1 DRIVE TRI STATE TTL CMOS SCHMITT DELAY PULL DOWN PULL UP GND VCC PAD 0 1 0 1 CELL CELL CELL CELL CLK RST CLK RST RST CLK RST CLK CLK RST RST CLK ...

Page 21: ...s in the AVR memory map are decoded into 16 select lines 8 for AT94K05 and are presented to the FPGA along with the AVR 8 bit data bus The FPGA can be used to create additional custom peripherals for the AVR microcontroller through this interface In addition there are 16 interrupt lines 8 for AT94K05 from the FPGA back into the AVR interrupt control ler Programmable peripherals or regular logic ca...

Page 22: ...edicated program SRAM 4 Kbytes x 8 dedicated data SRAM and 6 Kbytes x 16 or 12 Kbytes x 8 configurable SRAM which may be swapped between program and data memory spaces in 2 Kbytes x 16 or 4 Kbytes x 8 partitions For the AT94K05 the internal program and data SRAM is divided into three blocks 4 Kbytes 16 dedicated program SRAM 4 Kbytes x 8 dedicated data SRAM and 6 Kbytes x 16 or 12 Kbytes x 8 confi...

Page 23: ...ses addresses 0000 001F for the AVR CPU general working registers 001F 005F are the addresses used for Memory Mapped I O and store the information in dedicated reg isters Therefore on the FPGA side 0000 005F are available for data that is only needed by the FPGA 0000 07FF 27FF 3FFF 3800 3000 37FF 2800 2FFF 0FFF 1000 1FFF 2000 2FFF 3000 3FFF 005F Memory Partition is User Defined during Development ...

Page 24: ...ess being accessed by both devices at the same time the designer should add arbitration to the FPGA Logic to control who has priority In most cases the AVR would be used to restrict access by the FPGA using the FMXOR bit see Software Control Register SFTCR on page 51 You can read from the same location from both sides simultaneously SCR bit 38 controls the polarity of the clock to the SRAM from th...

Page 25: ...els are for layout the addressing scheme is transparent to AVR data read write System configuration determines the higher address for data memory SCR bits 41 0 40 0 no extra data memory SCR bits 41 0 40 1 data memory extended from 1000 1FFF SCR bits 41 1 40 0 data memory extended from 1000 2FFF SCR bits 41 1 40 1 data memory extended from 1000 3FFF Extended data memory is always lost to extended p...

Page 26: ...en this bit is set to 1 is dependent on how the SCR was initialized If the Enable FPGA SRAM Interface bit SCR63 in the SCR is 0 the FMXOR bit enables the FPGA SRAM Interface when set to 1 If the Enable FPGA SRAM Interface bit in the SCR is 1 the FMXOR bit disables the FPGA SRAM Interface when set to 1 Dur ing AVR reset the FMXOR bit is cleared by the hardware Even though the FPGA and AVR debug mod...

Page 27: ...FFF 2000 27FF MS Byte 10 5000 57FF 1800 1FFF LS Byte 11 5800 5FFF 1800 1FFF MS Byte 12 6000 67FF 1000 17FF LS Byte 13 6800 6FFF 1000 17FF MS Byte 14 7000 77FF 0800 0FFF LS Byte 15 7800 7FFF 0800 0FFF MS Byte 16 8000 87FF 0000 07FF LS Byte 17 n 8800 8FFF 0000 07FF MS Byte Table 8 AVR PC Addresses AVR PC Instruction 0FFE 9B28 0FFF CFFE 1000 B300 1001 9A39 Table 9 Frame Addresses Frame Address Frame ...

Page 28: ...ata Memory Write Using ST Instruction Figure 22 AVR SRAM Data Memory Read Using LD Instruction CLOCK RAMWE RAMADR DBUS DBUSOUT REGISTERED VALID ST cycle 1 ST cycle 2 next instruction VALID VALID CLOCK RAMRE RAMADR DBUS VALID LD cycle 1 LD cycle 2 next instruction VALID ...

Page 29: ...load or allow ing reconfigurable systems where the FPGA is updated algorithmically by the AVR For more information refer to the AT94K Series Configuration application note available on the Atmel web site at http www atmel com atmel acrobat doc2313 pdf Resets The user must have the flexibility to issue resets and reconfiguration commands to separate portions of the device There are two Reset pins o...

Page 30: ...0 SCR1 Reserved SCR2 0 Enable Cascading 1 Disable Cascading SCR2 controls the operation of the dual function I O CSOUT When SCR2 is set the CSOUT pin is not used by the configuration during downloads set this bit for configurations where two or more devices are cascaded together This applies for configuration to another FPSLIC device or to an FPGA SCR3 0 Check Function Enabled 1 Check Function Dis...

Page 31: ...t buffers driving the fast clocks The clock buffers are enabled and disabled synchronously with the rising edge of the respective FCK signal and stop in a High 1 state Setting one of these bits disables the appropriate FCK input buffer only and has no effect on the connection from the input buffer to the FPGA array SCR26 0 Disable On chip Debugger 1 Enable On chip Debugger JTAG Enable SCR27 must a...

Page 32: ...P0 pad SCR48 SCR53 Defaults dependent on package selected SCR49 0 EXT INT1 Driven By Port E 5 1 EXT INT1 Driven By INTP1 pad SCR48 SCR53 Defaults dependent on package selected SCR50 0 EXT INT2 Driven By Port E 6 1 EXT INT2 Driven By INTP2 pad SCR48 SCR53 Defaults dependent on package selected SCR51 0 EXT INT3 Driven By Port E 7 1 EXT INT3 Driven By INTP3 pad SCR48 SCR53 Defaults dependent on packa...

Page 33: ...SCR61 1 SCR60 0 Timer Oscillator Clock TOSC1 1 SCR61 1 SCR60 1 Watchdog Clock Global Clock 6 mux select set by using the AT94K Device Options in System Designer Note 1 The AS2 bit must be set in the ASSR register SCR62 0 Disable CacheLogic Writes to FPGA by AVR 1 Enable CacheLogic Writes to FPGA by AVR SCR63 0 Disable Access Read and Write to SRAM by FPGA 1 Enable Access Read and Write to SRAM by ...

Page 34: ...be accessed in one single instruction executed in one clock cycle The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers The embedded AVR core provides the following features 16 general purpose I O lines 32 x 8 general purpose working registers Real time Counter RTC 3 flexible timer counters with compare modes an...

Page 35: ...sters and Operands Rd Destination and source register in the register file Rr Source register in the register file R Result after instruction is executed K Constant data k Constant address b Bit in the register file or I O register 0 b 7 s Bit in the status register 0 s 2 X Y Z Indirect address register X R27 R26 Y R29 R28 and Z R31 R30 A I O location address q Displacement for direct addressing 0...

Page 36: ...BRNE Simple Instruction Set Summary Mnemonics Operands Description Operation Flags Clock Arithmetic and Logic Instructions ADD Rd Rr Add without Carry Rd Rd Rr Z C N V S H 1 ADC Rd Rr Add with Carry Rd Rd Rr C Z C N V S H 1 ADIW Rd K Add Immediate to Word Rd 1 Rd Rd 1 Rd K Z C N V S 2 SUB Rd Rr Subtract without Carry Rd Rd Rr Z C N V S H 1 SUBI Rd K Subtract Immediate Rd Rd K Z C N V S H 1 SBC Rd ...

Page 37: ... Call Subroutine PC k None 4 RET Subroutine Return PC STACK None 4 RETI Interrupt Return PC STACK I 4 CPSE Rd Rr Compare Skip if Equal if Rd Rr PC PC 2 or 3 None 1 2 3 CP Rd Rr Compare Rd Rr Z C N V S H 1 CPC Rd Rr Compare with Carry Rd Rr C Z C N V S H 1 CPI Rd K Compare with Immediate Rd K Z C N V S H 1 SBRC Rr b Skip if Bit in Register Cleared if Rr b 0 PC PC 2 or 3 None 1 2 3 SBRS Rr b Skip if...

Page 38: ...ata Transfer Instructions MOV Rd Rr Copy Register Rd Rr None 1 MOVW Rd Rr Copy Register Pair Rd 1 Rd Rr 1 Rr None 1 LDI Rd K Load Immediate Rd K None 1 LDS Rd k Load Direct from Data Space Rd k None 2 LD Rd X Load Indirect Rd X None 2 LD Rd X Load Indirect and Post Increment Rd X X X 1 None 2 LD Rd X Load Indirect and Pre Decrement X X 1 Rd X None 2 LD Rd Y Load Indirect Rd Y None 2 LD Rd Y Load I...

Page 39: ...n 1 Rd n Rd 0 0 C Rd 7 Z C N V H 1 LSR Rd Logical Shift Right Rd n Rd n 1 Rd 7 0 C Rd 0 Z C N V 1 ROL Rd Rotate Left Through Carry Rd 0 C Rd n 1 Rd n C Rd 7 Z C N V H 1 ROR Rd Rotate Right Through Carry Rd 7 C Rd n Rd n 1 C Rd 0 Z C N V 1 ASR Rd Arithmetic Shift Right Rd n Rd n 1 n 0 6 Z C N V 1 SWAP Rd Swap Nibbles Rd 3 0 Rd 7 4 None 1 BSET s Flag Set SREG s 1 SREG s 1 BCLR s Flag Clear SREG s 0 ...

Page 40: ...nputs Port E pins that are externally pulled Low will source current if the pull up resistors are activated Port E also serves the functions of various special features See Table 47 on page 149 The Port E pins are input with pull up when a reset condition becomes active even if the clock is not running RX0 Input receive to UART 0 See SCR52 TX0 Output transmit from UART 0 See SCR52 RX1 Input receiv...

Page 41: ...L1 and XTAL2 are input and output respectively of an inverting amplifier which can be configured for use as an on chip oscillator as shown in Figure 24 Either a quartz crystal or a ceramic resonator may be used Figure 24 Oscillator Connections External Clock To drive the device from an external clock source XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 25 Figure 25 Exte...

Page 42: ... word format meaning that every program memory address contains a single 16 bit instruction During interrupts and subroutine calls the return address program counter PC is stored on the stack The stack is effectively allocated in the general data SRAM as a consequence the stack size is only limited by the total SRAM size and the usage of the SRAM All user pro grams must initialize the Stack Pointe...

Page 43: ...so assigned a data memory address mapping the registers directly into the first 32 locations of the user Data Space Although not being physi cally implemented as SRAM locations this memory organization provides great flexibility in access of the registers as the X Y and Z registers can be set to index any register in the file The 4 to 16 Kbytes of data SRAM as configured during FPSLIC download are...

Page 44: ...e indirect addressing pointer registers The Indirect with Displacement mode features a 63 address locations reach from the base address given by the Y or Z register When using register indirect addressing modes with automatic Pre decrement and Post incre ment the address registers X Y and Z are decremented and incremented The entire data address space including the 32 general purpose working regis...

Page 45: ... address contained by the Z register i e the PC is loaded with the contents of the Z register Relative Program Addressing RJMP and RCALL Program execution continues at address PC k 1 The relative address k is 2048 to 2047 Memory Access Times and Instruction Execution Timing This section describes the general access timing concepts for instruction execution and inter nal memory access The AVR CPU i...

Page 46: ...e 30 Single Cycle ALU Operation The internal data SRAM access is performed in two system clock cycles as described in Figure 31 Figure 31 On chip Data SRAM Access Cycles AVR CLK 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch T1 T2 T3 T4 AVR CLK Total ExecutionTime Register Operands Fetc...

Page 47: ... Counter Register High Byte 78 2C 4C TCNT1L Timer Counter1 Counter Register Low Byte 78 2B 4B OCR1AH Timer Counter1 Output Compare Register A High Byte 79 2A 4A OCR1AL Timer Counter1 Output Compare Register A Low Byte 79 29 49 OCR1BH Timer Counter1 Output Compare Register B High Byte 79 28 48 OCR1BL Timer Counter1 Output Compare Register B Low Byte 79 27 47 TCCR2 FOC2 PWM2 COM21 COM20 CTC2 CS22 CS...

Page 48: ...36 FISUC FPGA I O Select Interrupt Mask Flag Register C Reserved on AT94K05 54 56 15 35 FISUB FPGA I O Select Interrupt Mask Flag Register B 54 56 14 34 FISUA FPGA I O Select Interrupt Mask Flag Register A 54 56 13 33 FISCR FIADR XFIS1 XFIS0 53 12 32 PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 124 11 31 DDRD DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 124 10 30 PIND PIND7 PIN...

Page 49: ...n SRAM All other instructions access the I O space through the 20 5F addressing For compatibility with future devices reserved bits should be written zero if accessed Reserved I O memory addresses should never be written The status flags are cleared by writing a logic 1 to them Note that the CBI and SBI instructions will operate on all bits in the I O register writing a one back into any flag read...

Page 50: ...n the register file by the BLD instruction Bit 5 H Half carry Flag The half carry flag H indicates a half carry in some arithmetic operations Bit 4 S Sign Bit S N V The S bit is always an exclusive or between the negative flag N and the two s complement overflow flag V Bit 3 V Two s Complement Overflow Flag The two s complement overflow flag V supports two s complement arithmetics Bit 2 N Negative...

Page 51: ...is dependent on how the SCR was initialized If the Enable Frame Interface bit in the SCR is 0 the FMXOR bit enables the Frame Interface when set to 1 If the Enable Frame Interface bit in the SCR is 1 the FMXOR bit disables the Frame Interface when set to 1 During AVR reset the FMXOR bit is cleared by the hardware Bit 2 WDTS Software Watchdog Test Clock Select When this bit is set to 1 the test clo...

Page 52: ...E bit just before the execution of the SLEEP instruction Bits 4 3 SM1 SM0 Sleep Mode Select Bits 1 and 0 This bit selects between the three available Sleep modes as shown in Table 12 Bit 2 PORF Power on Reset Flag This flag is set one upon power up of the device The flag can only be cleared zero by writ ing a zero to the PORF bit The bit will not be cleared by the hardware during AVR reset Bit 1 W...

Page 53: ...ach select line each qualified with either the FPGAIORE or FPGAIOWE strobe Refer to the FPGA AVR Interface section for more details Only the FISCR registers physically exist The FISUA D I O addresses for the purpose of FPGA I O selection are NOT supported by AVR Core I O space registers they are simply I O addresses available to 1 cycle IN OUT instructions which trigger appropriate enabling of the...

Page 54: ... D and extended to 16 with two bits from the FPGA I O Select Control Register XFIS1 and XFIS0 The FPGA I O read and write signals FPGAIORE and FPGAIOWE are qualified versions of the AVR IORE and IOWE sig nals Each will only be active if one of the four base I O addresses is accessed Reset all select lines become active and an FPGAIOWE strobe is enabled This is to allow the FPGA design to load zero...

Page 55: ...FISCR register out FISUA r17 select line 0 high Place data on AVR FPGA bus from r17 register out going data is assumed to be present in r17 before calling this subroutine ret io_select13_read ldi r16 0x01 FIADR 0 XFIS1 0 XFIS0 1 I O select line 13 out FISCR r16 load I O select values into FISCR register in r18 FISUD select line 13 high Read data on AVR FPGA bus which was placed into register FISUD...

Page 56: ... contention between the FPGA and another peripheral to start to drive active IORE at new address ver sus FPGAIORE Select n but since the AVR clock would have already captured the data from AVR DBUS FPGA Data Out this is a don t care situation AVR INST AVR CLOCK AVR IOWE AVR IOADR FISUA B C or D AVR DBUS FPGA DATA IN FPGA IOWE FPGA I O SELECT n FPGA CLOCK SET TO AVR SYSTEM CLOCK WRITE DATA VALID 1 ...

Page 57: ...PGA interrupt flag bit are set one the associated interrupt is executed Bits 7 4 FIF7 4 FPGA Interrupt Flags 7 4 See Bits 7 4 FIF3 0 FPGA Interrupt Flags 3 0 Bits 7 4 FIF11 8 FPGA Interrupt Flags 11 8 See Bits 7 4 FIF3 0 FPGA Interrupt Flags 3 0 Not available on the AT94K05 Bits 7 4 FIF15 12 FPGA Interrupt Flags 15 12 See Bits 7 4 FIF3 0 FPGA Interrupt Flags 3 0 Not available on the AT94K05 Bits 3...

Page 58: ...ndle Program Execution Starts Here 02 0002 FPGA_INT0 FPGA Interrupt0 Handle 03 0004 EXT_INT0 External Interrupt0 Handle 04 0006 FPGA_INT1 FPGA Interrupt1 Handle 05 0008 EXT_INT1 External Interrupt1 Handle 06 000A FPGA_INT2 FPGA Interrupt2 Handle 07 000C EXT_INT2 External Interrupt2 Handle 08 000E FPGA_INT3 FPGA Interrupt3 Handle 09 0010 EXT_INT3 External Interrupt3 Handle 0A 0012 TIM2_COMP Timer C...

Page 59: ...available on AT94K05 1D 0038 UART1_RXC UART1 Receive Complete Interrupt Handle 1E 003A UART1_DRE UART1 Data Register Empty Interrupt Handle 1F 003C UART1_TXC UART1 Transmit Complete Interrupt Handle 20 003E FPGA_INT12 FPGA Interrupt12 Handle not available on AT94K05 21 0040 FPGA_INT13 FPGA Interrupt13 Handle not available on AT94K05 22 0042 FPGA_INT14 FPGA Interrupt14 Handle Not Available on AT94K...

Page 60: ...C jmp TIM1_OVF Timer Counter1 Overflow Interrupt Handle 001E jmp TIM0_COMP Timer Counter0 Compare Match Interrupt Handle 0020 jmp TIM0_OVF Timer Counter0 Overflow Interrupt Handle 0022 jmp FPGA_INT4 FPGA Interrupt4 Handle 0024 jmp FPGA_INT5 FPGA Interrupt5 Handle 0026 jmp FPGA_INT6 FPGA Interrupt6 Handle 0028 jmp FPGA_INT7 FPGA Interrupt7 Handle 002A jmp UART0_RXC UART0 Receive Complete Interrupt ...

Page 61: ...See IEEE 1149 1 JTAG Boundary scan on page 73 During reset all I O registers except the MCU Status register are then set to their Initial Val ues and the program starts execution from address 0000 The instruction placed in address 0000 must be a JMP absolute jump instruction to the reset handling routine If the program never enables an interrupt source the interrupt vectors are not used and regula...

Page 62: ...hreshold voltage VPOT regardless of the VCC rise time see Figure 36 and Figure 37 Figure 36 MCU Start up RESET Tied to VCC Figure 37 Watchdog Reset during Operation Table 16 Reset Characteristics VCC 3 3V Symbol Parameter Minimum Typical Maximum Units VPOT 1 Power on Reset Threshold Rising 1 0 1 4 1 8 V Power on Reset Threshold Falling 0 4 0 6 0 8 V VRST RESET Pin Threshold Voltage VCC 2 V TTOUT R...

Page 63: ...The embedded AVR core has one dedicated 8 bit Interrupt Mask control register TIMSK Timer Counter Interrupt Mask Register In addition other enable and mask bits can be found in the peripheral control registers When an interrupt occurs the Global Interrupt Enable I bit is cleared zero and all interrupts are disabled The user software can set one the I bit to enable nested interrupts The I bit is se...

Page 64: ...Counter1 CompareA Match interrupt is enabled The corresponding interrupt is exe cuted if a CompareA match in Timer Counter1 occurs i e when the OCF1A bit is set in the Timer Counter Interrupt Flag Register TIFR Bit 5 OCIE1B Timer Counter1 Output CompareB Match Interrupt Enable When the OCIE1B bit is set one and the I bit in the Status Register is set one the Timer Counter1 CompareB Match interrupt...

Page 65: ...the Timer Counter1 Overflow Interrupt is executed In PWM mode this bit is set when Timer Counter1 advances from 0000 Bit 6 OCF1A Output Compare Flag 1A The OCF1A bit is set one when compare match occurs between the Timer Counter1 and the data in OCR1A Output Compare Register 1A OCF1A is cleared by the hardware when exe cuting the corresponding interrupt handling vector Alternatively OCF1A is clear...

Page 66: ...ogic 1 to the flag When the I bit in SREG and OCIE0 Timer Counter2 Compare Interrupt Enable and the OCF0 are set one the Timer Counter0 Output Compare Interrupt is executed Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles mini mum Four clock cycles after the interrupt flag has been set the program vector address for the actual interru...

Page 67: ...ator is voltage dependent When waking up from Power down mode there is a delay from the wake up condition occurs until the wake up becomes effective This allows the clock to restart and become stable after having been stopped The wake up period is defined by the same time set bits that define the reset time out period The wake up period is equal to the clock reset period as shown in Figure 22 on p...

Page 68: ...tween the TDI input and TDO output The Instruction Register holds JTAG instructions controlling the behavior of a Data Register Of the Data Registers the ID Register Bypass Register and the AVR I O Boundary Scan Chain are used for board level testing The Internal Scan Chain and Break Point Scan Chain are used for On Chip debugging only The Test Access Port TAP The JTAG interface is accessed throug...

Page 69: ...RFACE BREAKPOINT UNIT FLOW CONTROL UNIT OCD STATUS AND CONTROL INTERNAL SCAN CHAIN M U X JTAG INSTRUCTION REGISTER DEVICE ID REGISTER BYPASS REGISTER PC Instruction BREAKPOINT SCAN CHAIN ADDRESS DECODER PORT E 2 wire Serial AVR BOUNDARY SCAN CHAIN DEVICE BOUNDARY PROGRAM DATA SRAM M U X AVR RESET SCAN CHAIN FPGA AVR SCAN CHAIN FPGA SRAM SCAN CHAIN RESET CONTROL UNIT ...

Page 70: ...the signal present on TMS shown adjacent to each state transition at the time of the rising edge at TCK The initial state after a Power On Reset is Test Logic Reset As a definition in this document the LSB is shifted in and out first for all shift registers Test Logic Reset Run Test Idle Shift DR Exit1 DR Pause DR Exit2 DR Update DR Select IR Scan Capture IR Shift IR Exit1 IR Pause IR Exit2 IR Upd...

Page 71: ...Run Test Idle state If the selected Data Register has a latched parallel output the latching takes place in the Update DR state The Exit DR Pause DR and Exit2 DR states are only used for navigating the state machine As shown in Figure 40 on page 70 the Run Test Idle 1 state need not be entered between selecting JTAG instruction and using Data Registers and some JTAG instructions may select certain...

Page 72: ...ns are there fore irrelevant for the user of the On Chip Debug system The JTAG Enable bit must be set one in the System Control Register to enable the JTAG Test Access Port In addition the On chip Debug Enable bit must be set one The AVR Studio enables the user to fully control execution of programs on an AVR device with On Chip Debug capability AVR In Circuit Emulator or the built in AVR Instruct...

Page 73: ...sting interconnections and integrity of components on Printed Circuits Boards by using the 4 TAP signals only The four IEEE 1149 1 defined mandatory JTAG instructions IDCODE BYPASS SAM PLE PRELOAD and EXTEST as well as the AVR specific public JTAG instruction AVR_RESET can be used for testing the Printed Circuit Board Initial scanning of the data reg ister path will show the ID code of the device ...

Page 74: ...face for Boundary Scan using a JTAG TCK clock frequency higher than the internal chip frequency is possible The chip clock is not required to run Data Registers The Data Registers are selected by the JTAG instruction registers described in section Boundary scan Specific JTAG Instructions on page 75 The data registers relevant for Boundary Scan operations are Bypass Register Device Identification R...

Page 75: ...2 Figure 42 Reset Register Boundary scan Chain The Boundary scan Chain has the capability of driving and observing the logic levels on the AVR s digital I O pins See Boundary scan Chain on page 76 for a complete description Boundary scan Specific JTAG Instructions The instruction register is 4 bit wide supporting up to 16 instructions Listed below are the JTAG instructions useful for Boundary Scan...

Page 76: ...owever the output latches are not connected to the pins The Boundary Scan Chain is selected as Data Register The active states are Capture DR Data on the external pins are sampled into the Boundary Scan Chain Shift DR The Boundary Scan Chain is shifted by the TCK input Update DR Data from the Boundary Scan chain is applied to the output latches However the output latches are not connected to the p...

Page 77: ...l For Bi directional Port Pin with Pull up Function D Q D Q G 0 1 0 1 D Q D Q G 0 1 0 1 0 1 0 1 D Q D Q G 0 1 Port Pin PXn Vcc EXTEST To Next Cell ShiftDR Output Control OC Pullup Disable PLD Output Data OD Input Data ID From Last Cell UpdateDR ClockDR FF2 LD2 FF1 LD1 LD0 FF0 ...

Page 78: ...igure 43 replaces the dashed box in Figure 44 Figure 44 General Port Pin Schematic Diagram DATA BUS D D Q Q RESET RESET C C WD WP RD PULL UP PXn WP WD RL RP RD n WRITE PORTX WRITE DDRX READ PORTX LATCH READ PORTX PIN READ DDRX 0 7 DDXn PORTXn RL RP PUD PUD PULL UP DISABLE PLD OD OC ID PuD JTAG PULL UP DISABLE OC JTAG OUTPUT CONTROL OD JTAG OUTPUT DATA ID JTAG INPUT DATA ...

Page 79: ...nected outside the dashed box in Figure 44 to make the scan chain read the actual pin value Scanning AVR RESET Multiple sources contribute to the internal AVR reset therefore the AVR reset pin is not observed Instead the internal AVR reset signal output from the Reset Control Unit is observed see Figure 45 The scanned signal is active High if AVRResetn is Low and enabled or the device is in genera...

Page 80: ...or with external connection is supported in the scan chain The Enable signal is supported with a general boundary scan cell while the oscillator clock output is attached to an observe only cell In addition to the main clock the timer oscillator is scanned in the same way The output from the internal RC Oscillator is not scanned as this oscillator does not have external connections Figure 47 Bounda...

Page 81: ...lator is disabled Enable Clock bit is active Low FPSLIC Boundary scan Order Table 20 shows the Scan order between TDI and TDO when the Boundary Scan chain is selected as data path Bit 0 is the LSB the first bit scanned in and the first bit scanned out In Figure 43 Data Out In PXn corresponds to FF0 Enable Output PXn corresponds to FF1 and Pull up PXn corresponds to FF2 Table 20 AVR I O Boundary Sc...

Page 82: ...D2 29 Enable Output PD2 28 Pull up PD2 27 Data Out In PD1 26 Enable Output PD1 25 Pull up PD1 24 Data Out In PD0 23 Enable Output PD0 22 Pull up PD0 21 EXT INTERRUPTS Input with Pull up INTP3 20 1 Input with Pull up INTP2 19 1 Input with Pull up INTP1 18 1 Input with Pull up INTP0 17 1 UART1 Data Out In TX1 16 Enable Output TX1 15 Pull up TX1 14 Input with Pull up RX1 13 1 UART0 Data Out In TX0 12...

Page 83: ...abled Capture DR grabs pull up control from the AVR Capture DR grabs pull up control from the AVR Input with Pull up INTPn Observe only Capture DR grabs signal from pad Capture DR grabs signal from pad Data Out TXn Defines value driven if enabled Capture DR grabs signal on pad Capture DR always grabs 0 since Tx input is NC and tied to ground internally Enable Output TXn 1 output drive enabled Capt...

Page 84: ... Capture DR grabs clock enable from the AVR Capture DR grabs enable from the AVR Data Out In SDA Observe only Capture DR grabs signal from pad Capture DR grabs signal from pad Enable Output SDA 1 drive 0 0 drive disabled bus pull up Capture DR grabs output enable scan latch Capture DR grabs output enable from the AVR Clock Out In SCL Observe only Capture DR grabs signal from pad Capture DR grabs s...

Page 85: ...ock For the two Timer Counters 0 and 1 CK external source and stop can also be selected as clock sources Setting the PSR10 bit in SFIOR resets the prescaler This allows the user to operate with a predictable prescaler Note that Timer Counter1 and Timer Counter0 share the same prescaler and a prescaler reset will affect both Timer Counters Figure 48 Prescaler for Timer Counter0 and 1 The clock sour...

Page 86: ...on of Timer Counter2 on page 94 for a detailed description of asynchronous operation Bit 0 PSR10 Prescaler Reset Timer Counter1 and Timer Counter0 When this bit is set one the Timer Counter1 and Timer Counter0 prescaler will be reset The bit will be cleared by the hardware after the operation is performed Writing a zero to this bit will have no effect Note that Timer Counter1 and Timer Counter0 sh...

Page 87: ...NTROL REGISTER TCCR0 CS02 COM01 PWM0 CS01 COM00 CS00 CTC0 FOC0 PSR2 PSR10 SPECIAL FUNCTIONS IO REGISTER SFIOR T0 8 BIT DATA BUS 8 BIT ASYNCH T C2 DATA BUS ASYNCH STATUS REGISTER ASSR TIMER INT FLAG REGISTER TIFR TIMER COUNTER2 TCNT2 SYNCH UNIT 8 BIT COMPARATOR OUTPUT COMPARE REGISTER2 OCR2 TIMER INT MASK REGISTER TIMSK 0 0 0 7 7 7 T C CLK SOURCE UP DOWN T C CLEAR CONTROL LOGIC OCF2 TOV2 TOIE0 TOIE...

Page 88: ...ulse Width Modulators PWM In this mode the Timer Counter and the output compare register serve as a glitch free stand alone PWM with centered pulses See Timer Counter 0 and 2 in PWM Mode on page 91 for a detailed description on this function Timer Counter0 Control Register TCCR0 Timer Counter2 Control Register TCCR2 Bit 7 FOC0 FOC2 Force Output Compare Writing a logic 1 to this bit forces a change...

Page 89: ...s set to C the timer will count as follows if CTC0 CTC2 is set C 1 C 0 1 When the prescaler is set to divide by 8 the timer will count like this C 1 C 1 C 1 C 1 C 1 C 1 C 1 C 1 C C C C C C C C 0 0 0 0 0 0 0 0 1 1 1 In PWM mode this bit has a different function If the CTC0 or CTC2 bit is cleared in PWM mode the Timer Counter acts as an up down counter If the CTC0 or CTC2 bit is set one the Timer Co...

Page 90: ...itten to and a clock source is selected it continues counting in the timer clock cycle following the write operation Timer Counter0 Output Compare Register OCR0 Timer Counter2 Output Compare Register OCR2 Table 24 Clock 2 Prescale Select CS22 CS21 CS20 Description 0 0 0 Stop the Timer Counter2 is stopped 0 0 1 PCK2 0 1 0 PCK2 8 0 1 1 PCK2 32 1 0 0 PCK2 64 1 0 1 PCK2 128 1 1 0 PCK2 256 1 1 1 PCK2 1...

Page 91: ...selected the Timer Counter acts as an up down counter counting up from 00 to FF where it turns and counts down again to zero before the cycle is repeated When the counter value matches the contents of the Output Compare Reg ister the PE1 OC0 PWM0 or PE3 OC2 PWM2 pin is set or cleared according to the settings of the COMn1 COMn0 bits in the Timer Counter Control Registers TCCR0 or TCCR2 If CTC0 CTC...

Page 92: ...he up down PWM mode is selected the output PE1 OC0 PWM0 PE3 OC2 PWM2 is updated to Low or High on the next compare match according to the settings of COMn1 COMn0 This is shown in Table 26 In overflow PWM mode the output PE1 OC0 PWM0 PE3 OC2 PWM2 is held Low or High only when the Output Compare Register contains FF PWM Output OCn 1 PWM Output OCn 1 Unsynchronized OCn 1 Latch Synchronized OCn 1 Latc...

Page 93: ...written this bit becomes set one When TCNT2 has been updated from the temporary storage register this bit is cleared zero by the hardware A logic 0 in this bit indicates that TCNT2 is ready to be updated with a new value Bit 1 OCR2UB Output Compare Register2 Update Busy When Timer Counter2 operates asynchronously and OCR2 is written this bit becomes set one When OCR2 has been updated from the temp...

Page 94: ...ed When entering Power save mode after having written to TCNT2 OCR2 or TCCR2 the user must wait until the written register has been updated if Timer Counter2 is used to wake up the device Otherwise the MCU will go to sleep before the changes have had any effect This is extremely important if the Output Compare2 interrupt is used to wake up the device Output compare is disabled during write to OCR2...

Page 95: ...k and is not synchronized to the processor clock Timer Counter1 Figure 54 shows the block diagram for Timer Counter1 Figure 54 Timer Counter1 Block Diagram TOIE0 TOIE1 OCIE1A OCIE1B TICIE1 TOIE2 OCIE2 OCIE0 TOV0 TOV1 OCF1A OCF1B ICF1 TOV2 OCF2 OCF0 TIMER INT FLAG REGISTER TIFR CONTROL LOGIC TIMER COUNTER1 TCNT1 TIMER INT MASK REGISTER TIMSK T C1 INPUT CAPTURE REGISTER ICR1 T C1 OVER FLOW IRQ T C1 ...

Page 96: ...ful for lower speed functions or exact timing functions with infrequent actions The Timer Counter1 supports two Output Compare functions using the Output Compare Reg ister 1 A and B OCR1A and OCR1B as the data sources to be compared to the Timer Counter1 contents The Output Compare functions include optional clearing of the counter on compareA match and actions on the Output Compare pins on both c...

Page 97: ...ext compare match or forced compare match occurs The Force Output Compare bit can be used to change the out put pin without waiting for a compare match in the timer The automatic action programmed in COM1A1 and COM1A0 happens as if a Compare Match had occurred but no interrupt is gen erated and it will not clear the timer even if CTC1 in TCCR1B is set The FOC1A bit will always be read as zero The ...

Page 98: ...le This bit must be set by the user to enable the Input Capture Function of timer1 Disabling pre vents unnecessary register copies during normal use of the PE7 port Bit 4 Res Reserved Bit This bit is reserved in the FPSLIC and will always read zero Bit 3 CTC1 Clear Timer Counter1 on Compare Match When the CTC1 control bit is set one the Timer Counter1 is reset to 0000 in the clock cycle after a co...

Page 99: ...hen accessing OCR1A OCR1B and ICR1 If the main program and also interrupt routines perform access to registers using TEMP interrupts must be dis abled during access from the main program and interrupt routines TCNT1 Timer Counter1 Write When the CPU writes to the high byte TCNT1H the written data is placed in the TEMP regis ter Next when the CPU writes the low byte TCNT1L this byte of data is comb...

Page 100: ... software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match A compare match will set the compare interrupt flag in the CPU clock cycle following the com pare event Since the Output Compare Registers OCR1A and OCR1B are 16 bit registers a tempo rary register TEMP is used when OCR1A B are written to ensure that both bytes are updated simultaneously When the...

Page 101: ...a dual 8 9 or 10 bit free run ning glitch free and phase correct PWM with outputs on the PD6 OC1A and PE5 OC1B pins In this mode the Timer Counter1 acts as an up down counter counting up from 0000 to TOP see Table 30 where it turns and counts down again to zero before the cycle is repeated When the counter value matches the contents of the 8 9 or 10 least significant bits depends of the resolution...

Page 102: ...er TOP Values and PWM Frequency CTC1 PWM11 PWM10 PWM Resolution Timer TOP Value Frequency 0 0 1 8 bit 00FF 255 fTCK1 510 0 1 0 9 bit 01FF 511 fTCK1 1022 0 1 1 10 bit 03FF 1023 fTCK1 2046 1 0 1 8 bit 00FF 255 fTCK1 256 1 1 0 9 bit 01FF 511 fTCK1 512 1 1 1 10 bit 03FF 1023 fTCK1 1024 Table 31 Compare1 Mode Select in PWM Mode CTC1 1 COM1X1 1 COM1X0 1 Effect on OCX1 x 2 0 x 2 Not connected 0 1 0 Clear...

Page 103: ...TOP and the up down PWM mode is selected the out put OC1A OC1B is updated to Low or High on the next compare match according to the settings of COM1A1 COM1A0 or COM1B1 COM1B0 This is shown in Table 32 In overflow PWM mode the output OC1A OC1B is held Low or High only when the Output Compare Reg ister contains TOP Counter Value Compare Value PWM OutputOC1X 1 Synchronized OCR1X 1 Latch Counter Value...

Page 104: ...chip oscillator which runs at 1 MHz This is the typical value at VCC 3 3V See characterization data for typical values at other VCC lev els By controlling the Watchdog Timer prescaler the watchdog reset interval can be adjusted see Table 33 on page 105 for a detailed description The WDR watchdog reset instruction resets the Watchdog Timer Eight different clock cycle periods can be selected to dete...

Page 105: ...next four clock cycles write a logic 0 to WDE This disables the watchdog Bits 2 0 WDP2 WDP1 WDP0 Watchdog Timer Prescaler 2 1 and 0 The WDP2 WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled The different prescaling values and their corresponding Time out periods are shown in Table 33 Note 1 The frequency of the watchdog oscillator is voltage dependent a...

Page 106: ...o an arithmetic logic unit ALU The FPSLIC based AVR Core is designed to give FPSLIC the ability to effectively perform the same multiply accumulate operation The multiply accumulate operation sometimes referred to as multiply add operation has one critical drawback When adding multiple values to one result variable even when adding posi tive and negative values to some extent cancel each other the...

Page 107: ...7 r16 r1 r0 Move the result to the r17 r16 register pair Note the use of the MOVW instruction This example is valid for all of the multiply instructions Figure 59 Valid Register Usage Example 2 Special Cases This example shows some special cases of the MUL instruction that are valid lds r0 variableA Load r0 with SRAM variable A lds r1 variableB Load r1 with SRAM variable B mul r1 r0 r1 r0 variable...

Page 108: ...ated to a well defined 8 bit format see Using Fractional Numbers on page 111 16 bit Multiplication The new multiply instructions are specifically designed to improve 16 bit multiplication This section presents solutions for using the hardware multiplier to do multiplication with 16 bit operands Figure 60 schematically illustrates the general algorithm for multiplying two 16 bit numbers with a 32 b...

Page 109: ...used A 216 A and B 216 B C A B 216 A 216 B A B 232 216 A B Here we are only concerned with the 16 LSBs the last part of this sum will be discarded and we will get the correct result C A B Figure 61 16 bit Multiplication 16 bit Result When one factor is negative and one factor is positive for example A is negative and B is positive C A B 216 A B 216 B A B 216 A B 216 B 1 The MSBs will be discarded ...

Page 110: ... 1844 into r21 r20 callmul16x16_32 Call 16bits x 16bits 32bits multiply routine Figure 62 16 bit Multiplication 32 bit Result The 32 bit result of the unsigned multiplication of 672 and 1844 will now be in the registers R19 R18 R17 R16 If muls16x16_32 is called instead of mul16x16_32 a signed multiplica tion will be executed If mul16x16_16 is called the result will only be 16 bits long and will be...

Page 111: ...er than 2 the result will not be correct To fully understand the format of the fractional numbers a comparison with the integer num ber format is useful Table 20 illustrates the two 8 bit unsigned numbers formats Signed fractional numbers like signed integers use the familiar two s complement format Numbers in the range 1 1 may be represented using this format If the byte 1011 0010 is interpreted ...

Page 112: ...a 0 5 in the rest 0 8125 0 5 1 625 Yes 1 625 is higher than or equal to 1 Byte is now 11xx xxxx Is there a 0 25 in the rest 0 625 0 5 1 25 Yes 1 25 is higher than or equal to 1 Byte is now 111x xxxx Is there a 0 125 in the rest 0 25 0 5 0 5 No 0 5 is lower than 1 Byte is now 1110 xxxx Is there a 0 0625 in the rest 0 5 0 5 1 Yes 1 is higher than or equal to 1 Byte is now 1110 1xxx Since we do not h...

Page 113: ...ds is not 1 when using the FMULS instruction The 16 bit x 16 bit fractional multiply also has this restriction Example 5 Basic Usage 8 bit x 8 bit 16 bit Signed Fractional Multiply This example shows an assembly code that reads the port E input value and multiplies this value with a fractional constant 0 625 before storing the result in register pair R17 R16 in r16 PINE Read pin values ldi r17 B0 ...

Page 114: ...w r17 r16 r1 r0 mul r23 r20 ah bl add r17 r0 mul r21 r22 bh al add r17 r0 ret mul16x16_32 Description Unsigned multiply of two 16 bit numbers with a 32 bit result Usage R19 R18 R17 R16 R23 R22 R21 R20 Statistics Cycles 17 ret Words 13 ret Register usage R0 to R2 and R16 to R23 11 registers 1 Note 1 Full orthogonality i e any register pair can be used as long as the result and the two oper ands do ...

Page 115: ...mul r22 r20 al bl movw r17 r16 r1 r0 mulsu r23 r20 signed ah bl sbc r19 r2 Sign extend add r17 r0 adc r18 r1 adc r19 r2 mulsu r21 r22 signed bh al sbc r19 r2 Sign Extend add r17 r0 adc r18 r1 adc r19 r2 ret mac16x16_32 Description Signed multiply accumulate of two 16 bit numbers with a 32 bit result Usage R19 R18 R17 R16 R23 R22 R21 R20 Statistics Cycles 23 ret Words 19 ret Register usage R0 to R2...

Page 116: ...2 ret mac16x16_32_method_B uses two temporary registers r4 r5 Speed Size Optimized but reduces cycles words by 1 clr r2 muls r23 r21 signed ah signed bh movw r5 r4 r1 r0 mul r22 r20 al bl add r16 r0 adc r17 r1 adc r18 r4 adc r19 r5 mulsu r23 r20 signed ah bl sbc r19 r2 Sign extend add r17 r0 adc r18 r1 adc r19 r2 mulsu r21 r22 signed bh al sbc r19 r2 Sign extend add r17 r0 adc r18 r1 adc r19 r2 re...

Page 117: ...22 r20 al bl 1 adc r18 r2 movw r17 r16 r1 r0 fmulsu r23 r20 signed ah bl 1 sbc r19 r2 Sign extend add r17 r0 adc r18 r1 adc r19 r2 fmulsu r21 r22 signed bh al 1 sbc r19 r2 Sign extend add r17 r0 adc r18 r1 adc r19 r2 ret fmac16x16_32 Description Signed fractional multiply accumulate of two 16 bit numbers with a 32 bit result Usage R19 R18 R17 R16 R23 R22 R21 R20 1 Statistics Cycles 25 ret Words 21...

Page 118: ... adc r18 r4 adc r19 r5 fmulsu r23 r20 signed ah bl 1 sbc r19 r2 add r17 r0 adc r18 r1 adc r19 r2 fmulsu r21 r22 signed bh al 1 sbc r19 r2 add r17 r0 adc r18 r1 adc r19 r2 ret Comment on Implementations All 16 bit x 16 bit 32 bit functions implemented here start by clearing the R2 register which is just used as a dummy register with the add with carry ADC and subtract with carry SBC operations Thes...

Page 119: ...plete Multi processor Communication Mode Double Speed UART Mode Data Transmission A block schematic of the UART transmitter is shown in Figure 64 The two UARTs are identical and the functionality is described in general for the two UARTs Figure 64 UART Transmitter 1 Note 1 n 0 1 PE0 PE2 U2Xn 10 11 BIT TX SHIFT REGISTER PIN CONTROL LOGIC UART CONTROL AND STATUS REGISTER UCSRnA UART CONTROL AND STAT...

Page 120: ...er is cleared start bit and bit 9 or 10 is set stop bit If a 9 bit data word is selected the CHR9n bit in the UART Control and Status Register UCSRnB is set the TXB8 bit in UCSRnB is transferred to bit 9 in the Transmit shift register On the Baud rate clock following the transfer operation to the shift register the start bit is shifted out on the TXDn pin Then follows the data LSB first When the s...

Page 121: ...e first zero sample Following the 1 to 0 transition the receiver samples the RXDn pin at sam ples 8 9 and 10 If two or more of these three samples are found to be logic 1s the start bit is rejected as a noise spike and the receiver starts looking for the next 1 to 0 transition PE1 PE3 DATA BUS BAUD UART I O DATA REGISTER UDRn 10 11 BIT RX SHIFT REGISTER STORE UDRn 16 BAUD x 16 RXENn TXENn CHR9n RX...

Page 122: ...ransmit Data register is accessed If the 9 bit data word is selected the CHR9n bit in the UART Control and Status Register UCSRnB is set the RXB8n bit in UCSRnB is loaded with bit 9 in the Transmit shift register when data is transferred to UDRn If after having received a character the UDRn register has not been read since the last receive the OverRun ORn flag in UCSRnB is set This means that the ...

Page 123: ... MCUs are in Multi processor Communication Mode MPCMn in UCSRnA is set 2 The Master MCU sends an address byte and all Slaves receive and read this byte In the Slave MCUs the RXCn flag in UCSRnA will be set as normal 3 Each Slave MCU reads the UDRn register and determines if it has been selected If so it clears the MPCMn bit in UCSRnA otherwise it waits for the next address byte 4 For each received...

Page 124: ...pt to be executed TXCn is cleared by the hardware when executing the corresponding interrupt handling vector Alternatively the TXCn bit is cleared zero by writing a logic 1 to the bit Bit 5 UDRE0 UDRE1 UART Data Register Empty This bit is set one when a character written to UDRn is transferred to the Transmit shift regis ter Setting of this bit indicates that the transmitter is ready to receive a ...

Page 125: ...Communication Mode on page 123 UART0 Control and Status Registers UCSR0B UART1 Control and Status Registers UCSR1B Bit 7 RXCIE0 RXCIE1 RX Complete Interrupt Enable When this bit is set one a setting of the RXCn bit in UCSRnA will cause the Receive Com plete interrupt routine to be executed provided that global interrupts are enabled Bit 6 TXCIE0 TXCIE1 TX Complete Interrupt Enable When this bit is...

Page 126: ...9th data bit of the received character Bit 0 TXB80 TXB81 Transmit Data Bit 8 When CHR9n is set one TXB8n is the 9th data bit in the character to be transmitted Baud rate Generator The baud rate generator is a frequency divider which generates baud rates according to the following equation 1 BAUD Baud rate fCK Crystal Clock Frequency UBR Contents of the UBRRHI and UBRRn Registers 0 4095 Note 1 This...

Page 127: ...0 0 0 0000 01001111 04F 79 14400 14400 0 0 0000 00011101 01D 29 19200 19200 0 0 0000 00111011 03B 59 19200 19200 0 0 0000 00010011 013 19 28800 28880 0 3 0000 00100111 027 39 28800 28880 0 3 0000 00001110 00E 14 38400 38400 0 0 0000 00011101 01D 29 38400 38400 0 0 0000 00001001 009 9 57600 57600 0 0 0000 00010011 013 19 57600 57600 0 0 0000 00000111 007 7 72000 76800 6 7 0000 00001110 00E 14 76800...

Page 128: ...d in at least two of the three samples is taken as the bit value All bits are shifted into the transmitter shift register as they are sampled Sampling of an incoming character is shown in Figure 67 Figure 67 Sampling Received Data when the Transmission Speed is Doubled The Baud rate Generator in Double UART Speed Mode Note that the baud rate equation is different from the equation 1 at page 126 wh...

Page 129: ...0 00100111 027 39 28800 28880 0 3 0000 01001111 04F 79 28800 28880 0 3 0000 00011101 01D 29 38400 38400 0 0 0000 00111011 03B 59 38400 38400 0 0 0000 00010011 013 19 57600 57600 0 0 0000 00100111 027 39 57600 57600 0 0 0000 00001110 00E 14 76800 76800 0 0 0000 00011101 01D 29 76800 76800 0 0 0000 00001001 009 9 115200 115200 0 0 0000 00010011 013 19 115200 115200 0 0 0000 00000100 004 4 230400 230...

Page 130: ...ter Slave and Transmitter Receiver operation at up to 400 kHz bus clock rate The 2 wire Serial Interface has hardware support for the 7 bit addressing but is easily extended to 10 bit addressing format in software When operating in 2 wire Serial mode i e when TWEN is set a glitch filter is enabled for the input signals from the pins SCL and SDA and the output from these pins are slew rate controll...

Page 131: ...gister TWDR and the 2 wire Serial Address Register TWAR used in Slave mode The 2 wire Serial Bit rate Register TWBR Bit 7 6 5 4 3 2 1 0 1C 3C TWBR7 TWBR6 TWBR5 TWBR4 TWBR3 TWBR2 TWBR1 TWBR0 TWBR Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 ACK INPUT OUTPUT INPUT OUTPUT START STOP AND SYNC ARBITRATION TIMING AND CONTROL SERIAL CLOCK GENERATOR STATE MACHINE AND STATUS DEC...

Page 132: ...f the 2 wire Serial Interface so all accesses to the 2 wire Serial Address Register TWAR 2 wire Serial Status Register TWSR and 2 wire Serial Data Register TWDR must be com plete before clearing this flag Bit 6 TWEA 2 wire Serial Enable Acknowledge Flag TWEA flag controls the generation of the acknowledge pulse If the TWEA bit is set the ACK pulse is generated on the 2 wire Serial Bus if the follo...

Page 133: ...ire Serial Interrupt will be acti vated for as long as the TWINT flag is High The TWCR is used to control the operation of the 2 wire Serial Interface It is used to enable the 2 wire Serial Interface to initiate a Master access to generate a receiver acknowledge to generate a stop condition and control halting of the bus while the data to be written to the bus are written to the TWDR It also indic...

Page 134: ...ter to Slave Receiving the ACK flag is controlled by the 2 wire Serial Logic automatically the CPU cannot access the ACK bit directly The 2 wire Serial Slave Address Register TWAR Bits 7 1 TWA 2 wire Serial Slave Address Register These seven bits constitute the Slave address of the 2 wire Serial Bus interface unit Bit 0 TWGCE 2 wire Serial General Call Recognition Enable Bit This bit enables if se...

Page 135: ...ftware action For each status code the required software action and details of the following serial transfer are given in Table 41 to Table 45 Master Transmitter Mode In the Master Transmitter mode a number of data bytes are transmitter to a Slave Receiver see Figure 71 Before the Master Transmitter mode can be entered the TWCR must be initial ized as shown in Table 38 TWEN must be set to enable t...

Page 136: ...d START condition state 10 the 2 wire Serial Interface may switch to the Master Transmitter mode by loading TWDR with SLA W Slave Receiver Mode In the Slave Receiver mode a number of data bytes are received from a Master Transmitter see Figure 73 To initiate the Slave Receiver mode TWAR and TWCR must be initialized as follows The upper 7 bits are the address to which the 2 wire Serial Interface wi...

Page 137: ... deter mine the appropriate software action The appropriate action to be taken for each status code is detailed in Table 44 The Slave Transmitter mode may also be entered if arbitration is lost while the 2 wire Serial Interface is in the Master mode see state B0 If the TWEA bit is reset during a transfer the 2 wire Serial Interface will transmit the last byte of the transfer and enter state C0 or ...

Page 138: ...tion 0 1 0 1 0 0 1 1 1 1 1 1 X X X X Data byte will be transmitted and ACK or NOT ACK will be received Repeated START will be transmitted STOP condition will be transmitted and TWSTO flag will be reset STOP condition followed by a START condition will be transmitted and TWSTO flag will be reset 28 Data byte has been transmitted ACK has been received Load data byte or No TWDR action or No TWDR acti...

Page 139: ...lave mode MT MR Successfull transmission to a slave receiver Next transfer started with a repeated start condition Not acknowledge received after the slave address Not acknowledge received after a data byte Arbitration lost in slave address or data byte Arbitration lost and addressed as slave DATA A n From master to slave From slave to master Any number of data bytes and their associated acknowled...

Page 140: ... SLA R has been transmitted ACK has been received No TWDR action or No TWDR action 0 0 0 0 1 1 0 1 Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned 48 SLA R has been transmitted NOT ACK has been received No TWDR action or No TWDR action or No TWDR action 1 0 1 0 1 1 1 1 1 X X X Repeated START will be transmitted STOP condition will be tran...

Page 141: ... in slave mode MR MT Successfull reception from a slave receiver Next transfer started with a repeated start condition Not acknowledge received after the slave address Arbitration lost in slave address or data byte Arbitration lost and addressed as slave DATA A n From master to slave From slave to master Any number of data bytes and their associated acknowledge bits This number contained in TWSR c...

Page 142: ... 78 Arbitration lost in SLA R W as Master General call address has been received ACK has been returned No TWDR action or No TWDR action X X 0 0 1 1 0 1 Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned 80 Previously addressed with own SLA W data has been received ACK has been returned No TWDR action or No TWDR action X X 0 0 1 1 0 1 Data by...

Page 143: ...wn SLA will be recognized GCA will be recognized if GC 1 a START condition will be transmitted when the bus becomes free A0 A STOP condition or repeated START condition has been received while still addressed as Slave Read data byte or Read data byte or Read data byte or Read data byte 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 Switched to the not addressed Slave mode no recognition of own SLA or GCA Switche...

Page 144: ...and addressed as slave Reception of the general call address and one or more data bytes Last data byte received is not acknowledged n From master to slave From slave to master Any number of data bytes and their associated acknowledge bits This number contained in TWSR corresponds to a defined state of the 2 wire serial bus P or S DATA A 80 A0 P or S A A DATA A 70 90 98 A 78 P or S DATA A 90 A0 P o...

Page 145: ...d NOT ACK has been received No TWDR action or No TWDR action or No TWDR action or No TWDR action 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 Switched to the not addressed Slave mode no recognition of own SLA or GCA Switched to the not addressed Slave mode own SLA will be recognized GCA will be recognized if GC 1 Switched to the not addressed Slave mode no recognition of own SLA or GCA a START condition will b...

Page 146: ...d state of the 2 wire serial bus P or S DATA C0 DATA A A C8 P or S All 1 s A Table 45 Status Codes for Miscellaneous States Status Code TWSR Status of the 2 wire Serial Bus and 2 wire Serial Hardware Application Software Response Next Action Taken by 2 wire Serial Hardware To From TWDR To TWCR STA STO TWINT TWEA F8 No relevant state information available TWINT 0 No TWDR action No TWCR action Wait ...

Page 147: ... PortD Input Pins address PIND is not a register and this address enables access to the physical value on each PortD pin When reading PORTD the PortD Data Latch is read and when reading PIND the logical values present on the pins are read PortD as General Digital I O PDn General I O pin The DDDn bit in the DDRD register selects the direction of this pin If DDDn is set one PDn is configured as an o...

Page 148: ... write The PortE output buffers can sink 20 mA As inputs PortE pins that are externally pulled Low will source current if the pull up resistors are activated All PortE pins have alternate functions as shown in Table 47 Table 46 DDDn 1 Bits on PortD Pins DDDn 1 PORTDn 1 I O Pull up Comment 0 0 Input No Tri state High Z 0 1 Input Yes PDn will source current if external pulled low default 1 0 Output ...

Page 149: ...External Timer0 clock PE1 RX0 UART0 receive pin Output compare Timer0 PWM0 PE2 TX1 UART1 transmit pin PE3 RX1 UART1 receive pin Output compare Timer2 PWM2 PE4 INT0 external Interrupt0 input External Timer1 clock PE5 INT1 external Interrupt0 input Output compare Timer1B PWM1B PE6 INT2 external Interrupt0 input Output compare Timer1A PWM1A PE7 INT3 external Interrupt0 input Input capture Counter1 Bi...

Page 150: ... enabled by setting bit SCR53 in the FPSLIC System Control Register PortE Bit 3 UART1 Receive Pin Receive Data Data input pin for the UART1 When the UART1 receiver is enabled this pin is configured as an input regardless of the value of DDRE2 When the UART1 forces this pin to be an input a logic 1 in PORTE2 will turn on the internal pull up PortE Bit 4 7 External Interrupt sources 0 1 2 3 The PE4 ...

Page 151: ...ee Timer Counters on page 85 PortE Schematics Note that all port pins are synchronized The synchronization latches are however not shown in the figures Figure 76 PortE Schematic Diagram Pin PE0 PE0 TX0D DATA BUS GTS DL SCR 52 MOS PULL UP RL WL DDE0 Q D R PORTE0 Q D R RESET RESET WD RD RP GTS Global Tri state DL Configuration Download WL Write PORTE WD Write DDRE RL Read PORTE Latch RD Read DDRE RP...

Page 152: ...ESET RESET WD RD RP GTS Global Tri State DL Configuration Download WL Write PORTE WD Write DDRE RL Read PORTE Latch RD Read DDRE RP Read PORTE Pin RX0D UART 0 Receive Data SCR System Control Register OC0 PMW0 Timer Counter 0 Output Compare COM0 Timer Counter0 Control Bits RX0 RX0D SCR 52 0 1 MOS PULL UP OC0 PMW0 1 0 COM00 COM01 MOS PULL UP RESET DL ...

Page 153: ...T RESET WD RD RP GTS Global Tri State DL Configuration Download WL Write PORTE WD Write DDRE RL Read PORTE Latch RD Read DDRE RP Read PORTE Pin TX1D UART 1 Transmit Data TX1ENABLE UART 1 Transmit Enable SCR System Control Register TX1D GTS DL SCR 53 1 0 TX1ENABLE MOS PULL UP RESET DL TX1 MOS PULL UP TX1D SCR 53 TX1ENABLE DL RESET DL GTS ...

Page 154: ...RESET WD RD RP GTS Global Tri State DL Configuration Download WL Write PORTE WD Write DDRE RL Read PORTE Latch RD Read DDRE RP Read PORTE Pin RX1D UART 1 Receive Data SCR System Control Register OC2 PMW2 Timer Counter 2 Output Compare COM2 Timer Counter2 Control Bits RX1 RX1D SCR 53 0 1 MOS PULL UP OC2 PMW2 1 0 COM20 COM21 MOS PULL UP RESET DL ...

Page 155: ...4 Q D R RESET WD RD RP GTS Global Tri State DL Configuration Download WL Write PORTE WD Write DDRE RL Read PORTE Latch RD Read DDRE RP Read PORTE Pin extintp0 External Interrupt 0 SCR System Control Register T1 Timer Counter1 External Clock INTP0 extintp0 SCR 48 0 1 MOS PULL UP WL PORTE4 Q D R RESET T1 MOS PULL UP RESET DL ...

Page 156: ...bal Tri State DL Configuration Download WL Write PORTE WD Write DDRE RL Read PORTE Latch RD Read DDRE RP Read PORTE Pin extintp1 External Interrupt 1 SCR System Control Register OC1B Timer Counter1 Output Compare B COM1B Timer Counter1 B Control Bits INTP1 extintp1 SCR 49 0 1 MOS PULL UP WL PORTE5 Q D R RESET OC1B COM1B0 COM1B1 1 0 MOS PULL UP RESET DL ...

Page 157: ...bal Tri State DL Configuration Download WL Write PORTE WD Write DDRE RL Read PORTE Latch RD Read DDRE RP Read PORTE Pin extintp2 External Interrupt 2 SCR System Control Register OC1A Timer Counter1 Output Compare A COM1A Timer Counter1 A Control Bits INTP2 extintp2 SCR 50 0 1 MOS PULL UP WL PORTE6 Q D R RESET OC1A COM1A0 COM1A1 1 0 MOS PULL UP RESET DL ...

Page 158: ...Q D R RESET WD RD RP GTS Global Tri State DL Configuration Download WL Write PORTE WD Write DDRE RL Read PORTE Latch RD Read DDRE RP Read PORTE Pin extintp3 External Interrupt 3 SCR System Control Register ICP Timer Counter Input Capture Pin INTP3 extintp3 SCR 51 0 1 MOS PULL UP WL PORTE7 Q D R RESET ICP MOS PULL UP RESET DL ...

Page 159: ...ese or any other conditions beyond those listed under oper ating conditions is not implied Exposure to Abso lute Maximum Rating conditions for extended periods of time may affect device reliability Storage Temperature 65 C to 150 C Voltage 2 on Any Pin with Respect to Ground 0 5V to 5 0V Supply Voltage VCC 0 5V to 5 0V Maximum Soldering Temp 10 sec 1 16 in 250 C ESD RZAP 1 5K CZAP 100 pF 2000V DC ...

Page 160: ...Minimum 2 1 V IOH 12 mA VCC 3 0V 2 1 V IOH 16 mA VCC 3 0V 2 1 V VOL Low level Output Voltage IOL 4 mA VCC 3 0V 0 4 V IOL 12 mA VCC 3 0V 0 4 V IOL 16 mA VCC 3 0V 0 4 V RRST Reset Pull up 100 500 kΩ RI O I O Pin Pull up 35 120 kΩ IIH High level Input Current VIN VCC Maximum 10 µA With Pull down VIN VCC 75 150 300 µA IIL Low level Input Current VIN VSS 10 µA With Pull up VIN VSS 300 150 75 µA IOZH Hi...

Page 161: ...ies to Commercial and Industrial grade products only 2 Devices are guaranteed to initialize properly at 50 of the minimum current listed above A larger capacity power supply may result in a larger initialization current 3 Ramp up time is measured from 0 V DC to 3 6 V DC Peak current required lasts less than 2 ms and occurs near the internal power on reset threshold voltage Table 49 Power On Power ...

Page 162: ...xt cycle will be a read cycle if WE remains Low during rising edge of ME Figure 83 SRAM Read Cycle Timing Diagram Figure 84 SRAM Write Cycle Timing Diagram Frame Interface The FPGA Frame Clock phase is selectable see System Control Register FPGA AVR on page 30 This document refers to the clock at the FPGA Dual port SRAM interface as ME the relation of ME to data address and write enable does not c...

Page 163: ...rom Posedge ME 3 4 4 2 5 9 2 9 4 2 6 9 ns tMEH Minimum ME High 0 7 0 9 1 3 0 6 0 9 1 5 ns tMEl Minimum ME Low 0 6 0 8 1 1 0 6 0 8 1 3 ns Table 51 SRAM Write Cycle Timing Numbers Commercial 3 3V 10 Industrial 3 3V 10 Symbol Parameter Commercial Industrial Units Minimum Typical Maximum Minimum Typical Maximum tADS Address Setup 0 6 0 8 1 1 0 5 0 8 1 2 ns tADH Address Hold 0 7 0 9 1 3 0 6 0 9 1 5 ns ...

Page 164: ...re 3 9 5 2 8 1 3 6 5 2 8 8 ns tIXC Clock Delay From XTAL2 Pad to AVR Core Clock 2 8 3 7 6 3 2 5 3 7 6 9 ns tIXI Clock Delay From XTAL2 Pad to AVR I O Clock 3 5 4 7 7 5 3 2 4 7 7 8 ns tCFIR AVR Core Clock to FPGA I O Read Enable 5 3 6 6 7 9 4 4 6 6 9 2 ns tCFIW AVR Core Clock to FPGA I O Write Enable 5 2 6 6 7 9 4 4 6 6 9 2 ns tCFIS AVR Core Clock to FPGA I O Select Active 6 3 7 8 9 4 5 3 7 8 11 0 ...

Page 165: ...re 85 External Clock Drive Waveforms Table 53 External Clock Drive VCC 3 0V to 3 6V Symbol Parameter Minimum Maximum Units 1 tCLCL Oscillator Frequency 0 25 MHz tCLCL Clock Period 40 ns tCHCX High Time 15 ns tCLCX Low Time 15 ns tCLCH Rise Time 1 6 µs tCHCL Fall Time 1 6 µs VIL1 VIH1 ...

Page 166: ...Maximum x y w z x y 3 4 ns 1 Unit Load Fast Carry tPD Maximum y y 2 3 ns 1 Unit Load Fast Carry tPD Maximum x y 2 9 ns 1 Unit Load Fast Carry tPD Maximum y x 3 0 ns 1 Unit Load Fast Carry tPD Maximum x x 2 3 ns 1 Unit Load Fast Carry tPD Maximum w y 3 4 ns 1 Unit Load Fast Carry tPD Maximum w x 3 4 ns 1 Unit Load Fast Carry tPD Maximum z y 3 4 ns 1 Unit Load Fast Carry tPD Maximum z x 2 4 ns 1 Uni...

Page 167: ...IO 1 4 ns 1 Unit Load Repeater tPD Maximum L IO 1 4 ns 1 Unit Load All input IO characteristics measured from a VIH of 50 of VDD at the pad CMOS threshold to the internal VIH of 50 of VDD All output IO characteristics are measured as the average of tPDLH and tPDHL to the pad VIH of 50 of VDD Cell Function Parameter Path 25 Units Notes IO Input tPD Maximum pad x y 1 9 ns No Extra Delay Input tPD Ma...

Page 168: ...K40 1 2 1 5 1 9 ns ns Rising Edge Clock FCK Input Buffer tPD Maximum pad clock pad clock AT94K05 AT94K10 AT94K40 0 7 0 8 0 9 ns ns Rising Edge Clock Clock Column Driver tPD Maximum clock colclk clock colclk AT94K05 AT94K10 AT94K40 1 3 1 8 2 5 ns ns Rising Edge Clock Clock Sector Driver tPD Maximum colclk secclk colclk secclk AT94K05 AT94K10 AT94K40 1 0 1 0 1 0 ns ns Rising Edge Clock GSRN Input Bu...

Page 169: ...we 5 0 ns Pulse Width High Write tsetup Minimum wr addr setup we 5 3 ns Write thold Minimum wr addr hold we 0 0 ns Write tsetup Minimum din setup we 5 0 ns Write thold Minimum din hold we 0 0 ns Write thold Minimum oe hold we 0 0 ns Write Read tPD Maximum din dout 8 7 ns rd addr wr addr Read tPD Maximum rd addr dout 6 3 ns Read tPZX Maximum oe dout 2 9 ns Read tPXZ Maximum oe dout 3 5 ns Sync RAM ...

Page 170: ...84 FPGA I O TDI IO34 IO50 IO98 TDO IO38 IO54 IO102 TMS IO43 IO63 IO123 TCK IO44 IO64 IO124 Table 56 AT94K Pin List AT94K05 96 FPGA I O AT94K10 192 FPGA I O AT94K40 384 FPGA I O Packages PC84 TQ100 PQ144 PQ208 West Side GND GND GND 12 1 1 2 I O1 GCK1 A16 I O1 GCK1 A16 I O1 GCK1 A16 13 2 2 4 I O2 A17 I O2 A17 I O2 A17 14 3 3 5 I O3 I O3 I O3 4 6 I O4 I O4 I O4 5 7 I O5 A18 I O5 A18 I O5 A18 15 4 6 8...

Page 171: ... A21 I O28 A21 18 7 12 18 VCC 1 VCC 1 I O17 I O29 I O18 I O30 GND I O31 I O32 I O33 I O34 I O35 I O36 GND Table 56 AT94K Pin List Continued AT94K05 96 FPGA I O AT94K10 192 FPGA I O AT94K40 384 FPGA I O Packages PC84 TQ100 PQ144 PQ208 Notes 1 VCC is I O high voltage Please refer to the Designing in Split Power Supply Support for AT94KAL and AT94SAL Devices application note 2 VDD is core high voltag...

Page 172: ...20 28 I O51 I O52 I O19 I O27 I O53 15 21 29 I O20 I O28 I O54 22 30 GND I O29 I O55 31 I O30 I O56 32 I O57 I O58 I O59 I O60 VCC 1 GND I O61 I O62 I O63 Table 56 AT94K Pin List Continued AT94K05 96 FPGA I O AT94K10 192 FPGA I O AT94K40 384 FPGA I O Packages PC84 TQ100 PQ144 PQ208 Notes 1 VCC is I O high voltage Please refer to the Designing in Split Power Supply Support for AT94KAL and AT94SAL D...

Page 173: ...41 I O83 40 I O26 I O42 I O84 41 GND VCC 1 I O85 I O86 I O87 I O88 I O27 A28 I O43 A28 I O89 A28 27 18 28 42 I O28 I O44 I O90 19 29 43 GND Table 56 AT94K Pin List Continued AT94K05 96 FPGA I O AT94K10 192 FPGA I O AT94K40 384 FPGA I O Packages PC84 TQ100 PQ144 PQ208 Notes 1 VCC is I O high voltage Please refer to the Designing in Split Power Supply Support for AT94KAL and AT94SAL Devices applicat...

Page 174: ...O100 42 60 I O37 Not a User I O I O53 Not a User I O I O101 29 43 61 I O38 LDC TDO I O54 LDC TDO I O102 LDC TDO 37 30 44 62 GND I O103 I O104 I O105 I O106 I O107 I O108 VCC 1 GND I O39 I O55 I O109 63 I O40 I O56 I O110 64 I O57 I O111 65 I O58 I O112 66 Table 56 AT94K Pin List Continued AT94K05 96 FPGA I O AT94K10 192 FPGA I O AT94K40 384 FPGA I O Packages PC84 TQ100 PQ144 PQ208 Notes 1 VCC is I...

Page 175: ... O132 GND VCC 1 I O133 I O134 I O67 I O135 I O68 I O136 I O45 I O69 I O137 33 50 74 I O46 I O70 I O138 34 51 75 GND I O139 Table 56 AT94K Pin List Continued AT94K05 96 FPGA I O AT94K10 192 FPGA I O AT94K40 384 FPGA I O Packages PC84 TQ100 PQ144 PQ208 Notes 1 VCC is I O high voltage Please refer to the Designing in Split Power Supply Support for AT94KAL and AT94SAL Devices application note 2 VDD is...

Page 176: ... O155 I O156 VCC 1 GND I O157 I O158 I O159 I O160 I O161 I O162 GND I O79 I O163 I O80 I O164 VCC 1 VCC 1 I O53 TD4 I O81 TD4 I O165 TD4 46 43 60 86 I O54 TD3 I O82 TD3 I O166 TD3 47 44 61 87 Table 56 AT94K Pin List Continued AT94K05 96 FPGA I O AT94K10 192 FPGA I O AT94K40 384 FPGA I O Packages PC84 TQ100 PQ144 PQ208 Notes 1 VCC is I O high voltage Please refer to the Designing in Split Power Su...

Page 177: ...O189 67 97 I O62 I O94 I O190 68 98 I O63 TD0 I O95 TD0 I O191 TD0 50 47 69 99 I O64 GCK4 I O96 GCK4 I O192 GCK4 51 48 70 100 GND GND GND 52 49 71 101 CON CON CON 53 50 72 103 East Side Table 56 AT94K Pin List Continued AT94K05 96 FPGA I O AT94K10 192 FPGA I O AT94K40 384 FPGA I O Packages PC84 TQ100 PQ144 PQ208 Notes 1 VCC is I O high voltage Please refer to the Designing in Split Power Supply Su...

Page 178: ... PD5 PD5 59 86 126 PD6 PD6 PD6 60 87 127 PE4 PE4 PE4 61 61 88 128 PE5 PE5 PE5 62 62 89 129 VDD 2 VDD 2 VDD 2 63 63 90 130 GND GND GND 64 64 91 131 PE6 PE6 PE6 65 65 92 132 PE7 CHECK PE7 CHECK PE7 CHECK 66 66 93 133 PD7 PD7 PD7 67 94 134 Table 56 AT94K Pin List Continued AT94K05 96 FPGA I O AT94K10 192 FPGA I O AT94K40 384 FPGA I O Packages PC84 TQ100 PQ144 PQ208 Notes 1 VCC is I O high voltage Ple...

Page 179: ...4 I O65 95 Are Unbonded 3 I O97 144 Are Unbonded 3 I O193 288 Are Unbonded 3 North Side Testclock Testclock Testclock 75 76 109 159 GND GND GND 76 77 110 160 I O97 A0 I O145 A0 I O289 A0 77 78 111 161 I O98 GCK7 A1 I O146 GCK7 A1 I O290 GCK7 A1 78 79 112 162 I O99 I O147 I O291 113 163 Table 56 AT94K Pin List Continued AT94K05 96 FPGA I O AT94K10 192 FPGA I O AT94K40 384 FPGA I O Packages PC84 TQ1...

Page 180: ...I O308 I O155 I O309 169 I O156 I O310 170 I O311 I O312 GND GND GND 118 171 I O105 I O157 I O313 119 172 I O106 I O158 I O314 120 173 I O159 I O315 I O160 I O316 VCC 1 VCC 1 I O317 I O318 Table 56 AT94K Pin List Continued AT94K05 96 FPGA I O AT94K10 192 FPGA I O AT94K40 384 FPGA I O Packages PC84 TQ100 PQ144 PQ208 Notes 1 VCC is I O high voltage Please refer to the Designing in Split Power Supply...

Page 181: ... 2 VDD 2 VDD 2 2 89 128 183 I O113 A8 I O169 A8 I O337 A8 3 90 129 184 I O114 A9 I O170 A9 I O338 A9 4 91 130 185 I O339 I O340 I O341 I O342 GND I O115 I O171 I O343 92 131 186 I O116 I O172 I O344 93 132 187 Table 56 AT94K Pin List Continued AT94K05 96 FPGA I O AT94K10 192 FPGA I O AT94K40 384 FPGA I O Packages PC84 TQ100 PQ144 PQ208 Notes 1 VCC is I O high voltage Please refer to the Designing ...

Page 182: ...96 I O365 I O366 GND I O367 I O368 I O121 I O183 I O369 197 I O122 I O184 I O370 198 I O123 A12 I O185 A12 I O371 A12 7 96 138 199 I O124 A13 I O186 A13 I O372 A13 8 97 139 200 Table 56 AT94K Pin List Continued AT94K05 96 FPGA I O AT94K10 192 FPGA I O AT94K40 384 FPGA I O Packages PC84 TQ100 PQ144 PQ208 Notes 1 VCC is I O high voltage Please refer to the Designing in Split Power Supply Support for...

Page 183: ... 10 99 143 204 VCC 1 VCC 1 VCC 1 11 100 144 205 Table 56 AT94K Pin List Continued AT94K05 96 FPGA I O AT94K10 192 FPGA I O AT94K40 384 FPGA I O Packages PC84 TQ100 PQ144 PQ208 Notes 1 VCC is I O high voltage Please refer to the Designing in Split Power Supply Support for AT94KAL and AT94SAL Devices application note 2 VDD is core high voltage Please refer to the Designing in Split Power Supply Supp...

Page 184: ...5AJC AT94K10AL 25AQC AT94K10AL 25BQC AT94K10AL 25DQC 84J 100A 144L1 208Q1 Commercial 0 C 70 C AT94K10AL 25AJI AT94K10AL 25AQI AT94K10AL 25BQI AT94K10AL 25DQI 84J 100A 144L1 208Q1 Industrial 40 C 85 C 40 000 25 MHz AT94K40AL 25BQC AT94K40AL 25DQC 144L1 208Q1 Commercial 0 C 70 C AT94K40AL 25BQI AT94K40AL 25DQI 144L1 208Q1 Industrial 40 C 85 C Package Type 84J 84 lead Plastic J leaded Chip Carrier PL...

Page 185: ...t of Measure mm SYMBOL MIN NOM MAX NOTE Notes 1 This package conforms to JEDEC reference MS 018 Variation AF 2 Dimensions D1 and E1 do not include mold protrusion Allowable protrusion is 010 0 254 mm per side Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line 3 Lead coplanarity is 0 004 0 102 mm maximum A 4 191 4 572 A1 2...

Page 186: ...0 05 0 15 A2 0 95 1 00 1 05 D 15 75 16 00 16 25 D1 13 90 14 00 14 10 Note 2 E 15 75 16 00 16 25 E1 13 90 14 00 14 10 Note 2 B 0 17 0 27 C 0 09 0 20 L 0 45 0 75 e 0 50 TYP Notes 1 This package conforms to JEDEC reference MS 026 Variation AED 2 Dimensions D1 and E1 do not include mold protrusion Allowable protrusion is 0 25 mm per side Dimensions D1 and E1 are maximum plastic body size dimensions in...

Page 187: ...d protrusions Allowable protrusion is 0 25 mm per side D1 and E1 are maximum plastic body size dimensions including mold mismatch 4 Dimension b does not include Dambar protrusion Allowable Dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0 08 mm Dambar cannot be located on the lower radius or the foot Minimum space between protrusion and an adjacent l...

Page 188: ...ng is for general information only refer to JEDEC Drawing MS 129 Variation FA 1 for proper dimensions tolerances datums etc 2 The top package body size may be smaller than the bottom package size by as much as 0 15 mm 3 Dimensions D1 and E1 do not include mold protrusions Allowable protrusion is 0 25 mm per side D1 and E1 are maximum plastic body size dimensions including mold mismatch 4 Dimension...

Page 189: ...IC Rev 1138G FPSLI 11 03 Thermal Coefficient Table Package Style Lead Count Theta J A 0 LFPM Theta J A 225 LFPM Theta J A 500 LPFM Theta J C PLCC 84 37 30 25 12 TQFP 100 47 39 33 22 LQFP 144 33 27 23 8 5 PQFP 208 32 28 24 10 ...

Page 190: ...nd Data SRAM 22 Data SRAM Access by FPGA FPGAFrame Mode 24 SRAM Access by FPGA AVR 24 AVR Cache Mode 29 Resets 29 System Control 30 AVR Core and Peripherals 34 Instruction Set Nomenclature Summary 35 Complete Instruction Set Summary 36 Pin Descriptions 40 Clock Options 41 Architectural Overview 42 General purpose Register File 43 X register Y register and Z register 44 ALU Arithmetic Logic Unit 44...

Page 191: ...imer Counter1 95 Watchdog Timer 104 Multiplier 106 UARTs 119 2 wire Serial Interface Byte Oriented 130 I O Ports 147 AC DC Timing Characteristics 159 Absolute Maximum Ratings 159 DC and AC Operating Range 3 3V Operation 159 Power On Power Supply Requirements 161 FPSLIC Dual port SRAM Characteristics 162 External Clock Drive Waveforms 165 Packaging and Pin List Information 170 Packaging Information...

Page 192: ... Tokyo 104 0033 Japan TEL 81 3 3523 3551 FAX 81 3 3523 7581 Memory 2325 Orchard Parkway San Jose CA 95131 TEL 1 408 441 0311 FAX 1 408 436 4314 Microcontrollers 2325 Orchard Parkway San Jose CA 95131 TEL 1 408 441 0311 FAX 1 408 436 4314 La Chantrerie BP 70602 44306 Nantes Cedex 3 France TEL 33 2 40 18 18 18 FAX 33 2 40 18 19 60 ASIC ASSP Smart Cards Zone Industrielle 13106 Rousset Cedex France TE...

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