175
2467S–AVR–07/09
ATmega128
External Clock
External clocking is used by the synchronous slave modes of operation. The description in this
section refers to
for details.
External clock input from the XCK pin is sampled by a synchronization register to minimize the
chance of meta-stability. The output from the synchronization register must then pass through
an edge detector before it can be used by the transmitter and receiver. This process introduces
a two CPU clock period delay and therefore the maximum external XCK clock frequency is lim-
ited by the following equation:
Note that f
osc
depends on the stability of the system clock source. It is therefore recommended to
add some margin to avoid possible loss of data due to frequency variations.
Synchronous Clock
Operation
When Synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock input
(slave) or clock output (master). The dependency between the clock edges and data sampling or
data change is the same. The basic principle is that data input (on RxD) is sampled at the oppo-
site XCK clock edge of the edge the data output (TxD) is changed.
Figure 81.
Synchronous Mode XCK Timing.
The UCPOL bit UCRSC selects which XCK clock edge is used for data sampling and which is
used for data change. As
shows, when UCPOL is zero the data will be changed at ris-
ing XCK edge and sampled at falling XCK edge. If UCPOL is set, the data will be changed at
falling XCK edge and sampled at rising XCK edge.
f
XCK
f
OSC
4
-----------
<
RxD / TxD
XCK
RxD / TxD
XCK
UCPOL = 0
UCPOL = 1
Sample
Sample
