113
2467S–AVR–07/09
ATmega128
Figure 46.
16-bit Timer/Counter Block Diagram
Note:
Refer to
,
for Timer/Counter1
and 3 pin placement and description.
Registers
The
Timer/Counter
(TCNTn),
Output Compare Registers
(OCRnA/B/C), and
Input Capture Reg-
ister
(ICRn) are all 16-bit registers. Special procedures must be followed when accessing the 16-
bit registers. These procedures are described in the section
“Accessing 16-bit Registers” on
Timer/Counter Control Registers
(TCCRnA/B/C) are 8-bit registers and have no
CPU access restrictions. Interrupt requests (shorten as Int.Req.) signals are all visible in the
Timer Interrupt Flag Register
(TIFR) and
Extended Timer Interrupt Flag Register
(ETIFR). All
interrupts are individually masked with the
Timer Interrupt Mask Register
(TIMSK) and
Extended
Timer Interrupt Mask Register
(ETIMSK). (E)TIFR and (E)TIMSK are not shown in the figure
since these registers are shared by other timer units.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on
the Tn pin. The Clock Select logic block controls which clock source and edge the Timer/Counter
uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source
is selected. The output from the clock select logic is referred to as the timer clock (clk
T
n
).
The double buffered Output Compare Registers (OCRnA/B/C) are compared with the
Timer/Counter value at all time. The result of the compare can be used by the waveform gener-
ator to generate a PWM or variable frequency output on the Output Compare Pin (OCnA/B/C).
ICFx
(Int.Req.)
TOVx
(Int.Req.)
Clock Select
Timer/Counter
DATABUS
OCRxA
OCRxB
OCRxC
ICRx
=
=
=
TCNTx
Waveform
Generation
Waveform
Generation
Waveform
Generation
OCxA
OCxB
OCxC
Noise
Canceler
ICPx
=
Fixed
TOP
Values
Edge
Detector
Control Logic
=
0
TOP
BOTTOM
Count
Clear
Direction
OCFxA
(Int.Req.)
OCFxB
(Int.Req.)
OCFxC
(Int.Req.)
TCCRxA
TCCRxB
TCCRxC
( From Analog
Comparator Ouput )
Tx
Edge
Detector
( From Prescaler )
TCLK
