67
2467S–AVR–07/09
ATmega128
Ports as General
Digital I/O
The ports are bi-directional I/O ports with optional internal pull-ups.
shows a functional
description of one I/O port pin, here generically called Pxn.
Figure 30.
General Digital I/O
Note:
1. WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk
I/O
, SLEEP,
and PUD are common to all ports.
Configuring the Pin
Each port pin consists of three Register bits: DDxn, PORTxn, and PINxn. As shown in
Description for I/O Ports” on page 87
, the DDxn bits are accessed at the DDRx I/O address, the
PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,
Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input
pin.
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is
activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to
be configured as an output pin. The port pins are tri-stated when a Reset condition becomes
active, even if no clocks are running.
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven
high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port
pin is driven low (zero).
When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn}
= 0b11), an intermediate state with either pull-up enabled ({DDxn, PORTxn} = 0b01) or output
clk
RPx
RRx
WPx
RDx
WDx
PUD
SYNCHRONIZER
WDx:
WRITE DDRx
WPx:
WRITE PORTx
RRx:
READ PORTx REGISTER
RPx:
READ PORTx PIN
PUD:
PULLUP DISABLE
clk
I/O
:
I/O CLOCK
RDx:
READ DDRx
D
L
Q
Q
RESET
RESET
Q
Q
D
Q
Q
D
CLR
PORTxn
Q
Q
D
CLR
DDxn
PINxn
DATA BUS
SLEEP
SLEEP:
SLEEP CONTROL
Pxn
I/O
