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6174B–ATARM–07-Nov-05

AT91FR40162S Preliminary

14.4

Interrupts

Each parallel I/O can be programmed to generate an interrupt when a level change occurs. This
is controlled by the PIO_IER (Interrupt Enable) and PIO_IDR (Interrupt Disable) registers which
enable/disable the I/O interrupt by setting/clearing the corresponding bit in the PIO_IMR. When
a change in level occurs, the corresponding bit in the PIO_ISR (Interrupt Status) is set whether
the pin is used as a PIO or a peripheral and whether it is defined as input or output. If the corre-
sponding interrupt in PIO_IMR (Interrupt Mask) is enabled, the PIO interrupt is asserted.

When PIO_ISR is read, the register is automatically cleared.

14.5

User Interface

Each individual I/O is associated with a bit position in the Parallel I/O user interface registers.
Each of these registers are 32 bits wide. If a parallel I/O line is not defined, writing to the corre-
sponding bits has no effect. Undefined bits read zero.

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Summary of Contents for AT91FR40162S

Page 1: ...dvanced Power saving Features CPU and Peripherals Can be De activated Individually Fully Static Operation 0 Hz to 75 MHz Internal Frequency Range at VDDCORE 1 8V 85 C 2 7V to 3 6V I O Operating Range...

Page 2: ...D NUB NWR1 P14 TXD0 NBUSY P9 IRQ0 P5 TIOB1 P3 TCLK1 A16 P15 RXD0 P0 TCLK0 MCKI NRST P13 SCK0 D12 D14 VDDIO P25 MCK0 NWDOVF A3 NC NC D3 TMS GND TCK D8 NC NC NWE NWR0 A2 TDI D6 GND NC VDDCORE VDDIO NC P...

Page 3: ...reset must be driven low during reset for Flash to be used as boot memory AIC FIQ Fast Interrupt Request Input PIO controlled after reset IRQ0 IRQ2 External Interrupt Request Input PIO controlled aft...

Page 4: ...Reset Input Input Low Resets Flash to standard operating mode Power VDDIO Power Power All VDDIO VDDCORE and all GND pins MUST be connected to their respective supplies by the shortest route VDDCORE P...

Page 5: ...0 P15 RXD0 P20 SCK1 P21 TXD1 NTRI P22 RXD1 P16 P17 P18 P19 P23 P24 BMS Reset NRST WD Watchdog Timer NWDOVF P I O TC Timer Counter TC0 TC1 P0 TCLK0 P3 TCLK1 P6 TCLK2 P1 TIOA0 P2 TIOB0 P4 TIOA1 P5 TIOB1...

Page 6: ...ection of external memories and application specific peripherals The EBI supports 8 or 16 bit devices and can use two 8 bit devices to emulate a single 16 bit device The EBI implements the early read...

Page 7: ...Controller PIO controls up to 32 I O lines It enables the user to select specific pins for on chip peripheral input output functions and general purpose input out put signal pins The PIO controller ca...

Page 8: ...plexed with a general purpose I O line While NRST is active and after the reset the MCKO is valid and outputs an image of the MCK signal The PIO Controller must be programmed to use this pin as stand...

Page 9: ...using classical Flash programmers prior to board mounting To enter tri state mode the NTRI pin must be held low during the last 10 clock cycles before the rising edge of NRST For normal operation the...

Page 10: ...and minimizes system power consumption The 32 bit bus increases the effectiveness of the use of the ARM instruction set and the processing of data that is wider than 16 bits thus making optimal use of...

Page 11: ...accesses For each of these banks the user can program Number of wait states Number of data float times wait time after the access is finished to prevent any bus contention in case the device is too l...

Page 12: ...bility an Erase Suspend feature is offered This feature puts the erase cycle on hold for an indefinite period and allows the user to read data from or to write data to any other sector within the same...

Page 13: ...o be applied to MCKI After reset the Flash Memory Uploader immediately recopies itself into the internal SRAM and jumps to it The following operation requires this memory resource only External access...

Page 14: ...nd requires only a serial cable to connect the Host to the Target Communications can be selected on either COM1 or COM2 and the serial link speed is limited to 115200 bauds Because the serial link is...

Page 15: ...s method maximizes the efficiency of bit manipulation and enables modification of a register with a single non interruptible instruction replacing the costly read modify write operation Unused bits in...

Page 16: ...andling interrupts The AIC also features a spurious vector detection feature which reduces spurious interrupt han dling to a minimum and a protect mode that facilitates the debug capabilities 7 1 3 PI...

Page 17: ...lso features a Receiver Timeout register facilitating variable length frame support when it is working with the PDC and a Time guard register used when interfacing with slow remote equipment 7 2 2 TC...

Page 18: ...AM Bank Reserved On chip Device Reserved On chip Device External Devices Selected by NCS0 4M Bytes 1M Byte 1M Byte 1M Byte 1M Byte No No No No No Yes Address Function Size Abort Control 0xFFFFFFFF 0xF...

Page 19: ...FD0000 0xFFF03FFF 0xFFF00000 0xFFE03FFF 0xFFE00000 0xFFC00000 AIC WD PS PIO TC USART1 USART0 SF EBI Advanced Interrupt Controller Reserved WatchdogTimer Power Saving Parallel I O Controller Reserved T...

Page 20: ...space with the external 24 bit address bus The memory map is defined by programming the base address and page size of the external memories see EBI User Interface and the EBI Chip Select Register desc...

Page 21: ...A23 Address bus output Output D0 D15 Data bus input output I O NCS0 NCS3 Active low chip selects output Output CS4 CS7 Active high chip selects output Output NRD Read enable output Output NWR0 NWR1 Lo...

Page 22: ...23 configuration by default A20 A21 A22 CS4 A20 A21 CS5 CS4 A20 CS6 CS5 CS4 CS7 CS6 CS5 CS4 Figure 10 2 Memory Connections for Four External Devices Note For four external devices the maximum address...

Page 23: ...4 shows how to connect a 512K x 8 bit memory on NCS2 Figure 10 4 Memory Connection for an 8 bit Data Bus Figure 10 5 shows how to connect a 512K x 16 bit memory on NCS2 Figure 10 5 Memory Connection f...

Page 24: ...yte writes The signal NWR0 NWE is used as NWR0 and enables lower byte writes The signal NRD NOE is used as NRD and enables half word and byte reads Figure 10 6 shows how to connect two 512K x 8 bit de...

Page 25: ...word Access Figure 10 8 shows how to connect a 16 bit device without byte access e g Flash on NCS2 Figure 10 8 Connection for a 16 bit Data Bus without Byte Write Capability EBI D0 D7 D8 D15 A1 A19 NL...

Page 26: ...presents NWE NWR0 and NWR1 unless NWR0 and NWR1 are otherwise represented ADDR represents A0 A23 and or A1 A23 10 7 1 Standard Read Protocol Standard read protocol implements a read cycle in which NRD...

Page 27: ...e cycle between consecutive accesses of the same type or between external and internal memory accesses Early read wait states affect the external bus only They do not affect internal bus timing Figure...

Page 28: ...NWE pin is used to control the output data timing to guarantee this operation It is therefore necessary to avoid excessive loading of the NWE pins which could delay the write signal too long and cause...

Page 29: ...d the number of cycles during which the NWE pulse is held low 0 wait states 1 2 cycle 1 wait state 1 cycle For each additional wait state programmed an additional cycle is added Figure 10 13 One Wait...

Page 30: ...accesses to the same external memory do not have added Data Float wait states Figure 10 14 Data Float Output Time Notes 1 Early Read Protocol 2 Standard Read Protocol 10 9 3 External Wait The NWAIT in...

Page 31: ...s automatically inserted when consecutive accesses are made to two different external memories if no wait states have already been inserted If any wait states have already been inserted e g data float...

Page 32: ...10 20 show examples of the two alternative protocols for external memory read access Figure 10 17 Standard Read Protocol without tDF Read Mem 1 Write Mem 1 Read Mem 1 Read Mem 2 Write Mem 2 Read Mem...

Page 33: ...8 Early Read Protocol Without tDF Read Mem 1 Write Mem 1 A0 A23 NRD NWE NCS1 NCS2 D0 D15 Mem 1 D0 D15 Mem 2 D0 D15 AT91 MCK Early Read Wait Cycle Read Mem 1 Read Mem 2 Write Mem 2 Early Read Wait Cycl...

Page 34: ...Standard Read Protocol with tDF Read Mem 1 Write Mem 1 A0 A23 NRD NWE NCS1 NCS2 D0 D15 Mem 1 D0 D15 Mem 2 D0 D15 AT91 MCK Data Float Wait Read Mem 1 Data Float Wait Read Mem 2 Read Mem 2 Data Float W...

Page 35: ...Read Protocol With tDF Read Mem 1 Write Mem 1 A0 A23 NRD NWE NCS1 NCS2 D0 D15 Mem 1 D0 D15 Mem 2 D0 D15 AT91 MCK Data Float Wait Early Read Wait Read Mem 1 Data Float Wait Read Mem 2 Read Mem 2 Data...

Page 36: ...1FR40162S external memory devices The configurations described are shown in the following table Table 10 3 Memory Access Waveforms Figure Number Number of Wait States Bus Width Size of Data Transfer F...

Page 37: ...it States 16 bit Bus Width Word Transfer ADDR ADDR 1 B2B1 B4 B3 B4 B3 B2 B1 MCK A1 A23 NCS NRD D0 D15 Internal Bus X X B2 B1 READ ACCESS NRD B2 B1 B4 B3 D0 D15 WRITE ACCESS NWE B2 B1 B4 B3 D0 D15 NLB...

Page 38: ...t Bus Width Word Transfer ADDR ADDR 1 B2B1 B4 B3 X X B2 B1 B4 B3 B2 B1 1 Wait State 1 Wair State MCK A1 A23 NCS NRD D0 D15 Internal Bus WRITE ACCESS READ ACCESS NRD D0 D15 Standard Protocol Early Prot...

Page 39: ...e 10 23 1 Wait State 16 bit Bus Width Half word Transfer B2 B1 1 Wait State MCK A1 A23 NCS NRD D0 D15 Internal Bus X X B2 B1 READ ACCESS Standard Protocol NLB NUB Early Protocol B2 B1 NRD D0 D15 WRITE...

Page 40: ...it Bus Width Word Transfer ADDR ADDR 1 X B1 X B3 B2 B1 MCK A0 A23 NCS NRD D0 D15 Internal Bus ADDR 2 ADDR 3 X X B2 B1 X B2 X X X B1 X B3 X B4 B4 B3 B2 B1 READ ACCESS Standard Protocol Early Protocol N...

Page 41: ...5 1 Wait State 8 bit Bus Width Half word Transfer ADDR X B1 1 Wait State MCK A0 A23 NCS NRD D0 D15 Internal Bus ADDR 1 1 Wait State X X B2 B1 X B2 X X X B1 READ ACCESS Standard Protocol Early Protocol...

Page 42: ...162S Preliminary Figure 10 26 1 Wait State 8 bit Bus Width Byte Transfer XB1 1 Wait State MCK A0 A23 NCS NRD D0 D15 Internal Bus X X X B1 READ ACCESS Standard Protocol Early Protocol D0 D15 X B1 WRITE...

Page 43: ...e Transfer MCK A1 A23 NCS NWR1 D0 D15 X B1 B2X ADDR X X X 0 ADDR X X X 0 ADDR X X X 0 ADDR X X X 1 Internal Address Internal Bus X X X B1 X X B2X NLB NUB READ ACCESS Standard Protocol NRD Early Protoc...

Page 44: ...ddress 0xFFE00000 Code Label EBI_BASE Notes 1 8 bit boot if BMS is detected high 2 16 bit boot if BMS is detected low Table 10 4 EBI Memory Map Offset Register Name Access Reset State 0x00 Chip Select...

Page 45: ...Wait state generation is disabled No wait states are inserted 1 Wait state generation is enabled 31 30 29 28 27 26 25 24 BA 23 22 21 20 19 18 17 16 BA 15 14 13 12 11 10 9 8 CSEN BAT TDF PAGES 7 6 5 4...

Page 46: ...red by the EBI decoder PAGES Page Size Active Bits in Base Address Code Label EBI_PAGES 0 0 1M Byte 12 Bits 31 20 EBI_PAGES_1M 0 1 4M Bytes 10 Bits 31 22 EBI_PAGES_4M 1 0 16M Bytes 8 Bits 31 24 EBI_PA...

Page 47: ...Name EBI_RCR Access Type Write only Absolute Address 0xFFE00020 Offset 0x20 RCB Remap Command Bit Code Label EBI_RCB 0 No effect 1 Cancels the remapping performed at reset of the page zero memory devi...

Page 48: ...20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DRP ALE ALE Valid Address Bits Maximum Addressable Space Valid Chip Select Code Label EBI_ALE 0 X X A20 A21 A22 A23 16M Bytes None EBI_ALE_16M 1 0...

Page 49: ...ent of entering the three byte program sequence is offered to further improve programming time After entering the six byte code only single pulses on the write control lines are required for writ ing...

Page 50: ...es are entered into the device The command sequences are shown in the Command Definition Table on page 61 I O8 I O15 are don t care inputs for the command codes The command sequences are written by ap...

Page 51: ...E edge of the sixth cycle while the 30H data input command is latched on the rising edge of WE The sector erase starts after the rising edge of WE of the sixth cycle The erase operation is internally...

Page 52: ...ash Memory features Data Polling to indicate the end of a program cycle If the status configuration register is set to a 00 during a program cycle an attempted read of the last byte word loaded will r...

Page 53: ...g of data in the designated sectors once the feature has been enabled These sectors can contain secure code that is used to bring up the system Enabling the lockdown feature will allow the boot code t...

Page 54: ...cturer as Atmel It is accessed using a software operation For details see Software Product Identification Entry and Software Product Identification Exit on page 64 11 3 6 128 bit Protection Register T...

Page 55: ...can also be written when the part is in the product ID mode Once in the CFI Query mode the system can read CFI data at the addresses given in Table 11 5 Common Flash Interface Definition on page 66 T...

Page 56: ...within the sector being erased During chip erase a valid address is any non protected sector address 2 I O7 sqhould be rechecked even if I O5 1 because I O7 may change simultaneously with I O5 START R...

Page 57: ...in the sector being erased During chip erase a valid address is any non protected sector address 2 I O7 should be rechecked even if I O5 1 because I O7 may change simultaneously with I O5 START Read I...

Page 58: ...he toggle bit even if I O5 1 because the toggle bit may stop tog gling as I O5 changes to 1 START Read I O7 I O0 Read I O7 I O0 Toggle Bit Toggle I O3 I O5 1 Read I O7 I O0 Twice Toggle Bit Toggle Pro...

Page 59: ...ggle bit even if I O5 1 because the toggle bit may stop tog gling as I O5 changes to 1 START Read I O7 I O0 Read I O7 I O0 Toggle Bit Toggle I O3 I O5 1 Read I O7 I O0 Twice Toggle Bit Toggle Program...

Page 60: ...O7 I O7 I O6 I O5 1 I O3 2 I O2 RDY BUSY Configuration Register 00 01 00 01 00 01 00 01 00 01 00 01 Programming I O7 0 TOGGLE 0 0 1 0 Erasing 0 0 TOGGLE 0 0 TOGGLE 0 Erase Suspended Read Erasing Secto...

Page 61: ...les the user to program two words in parallel only when VPP 12V The Addresses Addr1 and Addr2 of the two words DIN1 and DIN2 must only differ in address A0 This command should be used during manufac t...

Page 62: ...when accessing the protection register i e A19 A8 0 Table 11 3 Protection Register Addressing Table 1 Word Use Block A7 A6 A5 A4 A3 A2 A1 A0 0 Factory A 1 0 0 0 0 0 0 1 1 Factory A 1 0 0 0 0 0 1 0 2...

Page 63: ...SA15 64K 32K 080000 08FFFF 40000 47FFF SA16 64K 32K 090000 09FFFF 48000 4FFFF SA17 64K 32K 0A0000 0AFFFF 50000 57FFF SA18 64K 32K 0B0000 0BFFFF 58000 5FFFF SA19 64K 32K 0C0000 0CFFFF 60000 67FFF SA20...

Page 64: ...e is read for A0 VIL Device Code is read for A0 VIH 3 The device does not remain in identification mode if powered down 4 The device returns to standard operation mode 5 Manufacturer Code 001FH Device...

Page 65: ...m 1 Notes 1 Data Format I O15 I O8 Don t Care I O7 I O0 Hex Address Format A11 A0 Hex A 1 and A11 A19 Don t Care 2 Sector Lockdown feature enabled LOAD DATA AA TO ADDRESS 555 LOAD DATA 55 TO ADDRESS A...

Page 66: ...word write 12 s 20h 40h 0000h 21h 42h 000Ah Typ block erase 1 000 ms 22h 44h 0010h Typ chip erase 25 000 ms 23h 46h 0004h Max word write typ time 24h 48h 0000h N A 25h 4Ah 0002h Max block erase typ bl...

Page 67: ...protection bits supported 0 no 1 yes 47h 8Eh 0000h top or 0001h bottom Bit 8 top 0 or bottom 1 boot block device undefined bits are 0 48h 90h 0000h Bit 0 4 word linear burst with wrap around 0 no 1 y...

Page 68: ...ipheral integrated in the AT91FR40162S can be individually enabled and disabled by writing to the Peripheral Clock Enable PS_PCER and Peripheral Clock Disable Registers PS_PCDR The status of the perip...

Page 69: ...4000 Code Label PS_BASE Table 12 1 PS Memory Map Offset Register Name Access Reset State 0x00 Control Register PS_CR Write only 0x04 Peripheral Clock Enable Register PS_PCER Write only 0x08 Peripheral...

Page 70: ...gister Name PS_CR Access Write only Offset 0x00 CPU CPU Clock Disable 0 No effect 1 Disables the CPU clock The CPU clock is re enabled by any enabled interrupt or by hardware reset 31 30 29 28 27 26 2...

Page 71: ...s the USART 1 clock TC0 Timer Counter 0 Clock Enable 0 No effect 1 Enables the Timer Counter 0 clock TC1 Timer Counter 1 Clock Enable 0 No effect 1 Enables the Timer Counter 1 clock TC2 Timer Counter...

Page 72: ...the USART 1 clock TC0 Timer Counter 0 Clock Disable 0 No effect 1 Disables the Timer Counter 0 clock TC1 Timer Counter 1 Clock Disable 0 No effect 1 Disables the Timer Counter 1 clock TC2 Timer Count...

Page 73: ...TC0 Timer Counter 0 Clock Status 0 Timer Counter 0 clock is disabled 1 Timer Counter 0 clock is enabled TC1 Timer Counter 1 Clock Status 0 Timer Counter 1 clock is disabled 1 Timer Counter 1 clock is...

Page 74: ...s IRQ0 to IRQ2 The 8 level priority encoder allows the customer to define the priority between the different NIRQ interrupt sources Internal sources are programmed to be level sensitive or edge trigge...

Page 75: ...RQ USART Channel 1 interrupt 4 TC0IRQ Timer Channel 0 interrupt 5 TC1IRQ Timer Channel 1 interrupt 6 TC2IRQ Timer Channel 2 interrupt 7 WDIRQ Watchdog interrupt 8 PIOIRQ Parallel I O Controller interr...

Page 76: ...of the current interrupt at the time the reg ister AIC_IVR is read the interrupt which will be serviced In the case when a higher priority unmasked interrupt occurs while an interrupt already exists...

Page 77: ...e program counter with the interrupt handler address stored in the AIC_FVR register ldr PC PC F20 Alternatively the interrupt handler can be stored starting from address 0x0000001C as described in the...

Page 78: ...ctor would be returned In either case an End of Interrupt command would be necessary to acknowledge and to restore the context of the AIC This operation is generally not performed by the debug system...

Page 79: ...ne on the processor Even if vectoring is not used AIC_IVR must be read in order to de assert NIRQ Automatically clear the interrupt if it has been programmed to be edge triggered Push the current leve...

Page 80: ...interrupt service routine address and the fast interrupt is enabled The Instruction at address 0x1C FIQ exception vector address is ldr pc pc F20 Nested Fast Interrupts are not needed by the user Whe...

Page 81: ...masking or unmasking the fast interrupt depending on the state saved in the SPSR The F bit in the SPSR is significant If it is set it indicates that the ARM core was just about to mask FIQ interrupts...

Page 82: ...1 Read Write 0 Read Write 0 0x0FC Source Vector Register 31 AIC_SVR31 Read Write 0 0x100 IRQ Vector Register AIC_IVR Read only 0 0x104 FIQ Vector Register AIC_FVR Read only 0 0x108 Interrupt Status Re...

Page 83: ...positive or negative level sensitive or positive or negative edge triggered The active level or edge is not programmable for the internal sources 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14...

Page 84: ...t Value 0 Offset 0x100 IRQV Interrupt Vector Register The IRQ Vector Register contains the vector programmed by the user in the Source Vector Register corresponding to the current interrupt The Source...

Page 85: ...Register 0 which corresponds to FIQ 13 13 5 AIC Interrupt Status Register Register Name AIC_ISR Access Type Read only Reset Value 0 Offset 0x108 IRQID Current IRQ Identifier Code Label AIC_IRQID The I...

Page 86: ...ster Register Name AIC_IMR Access Type Read only Reset Value 0 Offset 0x110 Interrupt Mask 0 Corresponding interrupt is disabled 1 Corresponding interrupt is enabled 31 30 29 28 27 26 25 24 23 22 21 2...

Page 87: ...IC_NIRQ 0 NIRQ line inactive 1 NIRQ line active 13 13 9 AIC Interrupt Enable Command Register Register Name AIC_IECR Access Type Write only Offset 0x120 Interrupt Enable 0 No effect 1 Enables correspo...

Page 88: ...mmand Register Register Name AIC_ICCR Access Type Write only Offset 0x128 Interrupt Clear 0 No effect 1 Clears corresponding interrupt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IRQ2 IRQ1 IRQ0 15...

Page 89: ...0x130 The End of Interrupt Command Register is used by the interrupt routine to indicate that the interrupt treatment is complete Any value can be written because it is only necessary to make a write...

Page 90: ...AIC_SPU Access Type Read Write Reset Value 0 Offset 0x134 SPUVEC Spurious Interrupt Vector Handler Address The user may store the address of the spurious interrupt handler in this register 31 30 29 28...

Page 91: ...ether the pin is controlled by the corresponding peripheral or by the PIO Controller If a pin is a general purpose parallel I O pin not multiplexed with a peripheral PIO_PER and PIO_PDR have no effect...

Page 92: ...responding bit in the PIO_ISR Interrupt Status is set whether the pin is used as a PIO or a peripheral and whether it is defined as input or output If the corre sponding interrupt in PIO_IMR Interrupt...

Page 93: ...4 1 Parallel I O Multiplexed with a Bi directional Signal Pad PIO_OSR 1 0 1 0 PIO_PSR PIO_ODSR 1 0 0 1 PIO_PSR Event Detection PIO_PDSR PIO_ISR PIO_IMR Peripheral Output Enable Peripheral Output Perip...

Page 94: ...External Interrupt 0 Input PIO Input 60 10 P10 IRQ1 External Interrupt 1 Input PIO Input 63 11 P11 IRQ2 External Interrupt 2 Input PIO Input 64 12 P12 FIQ Fast Interrupt Input PIO Input 66 13 P13 SCK0...

Page 95: ...ead only 0x01FFFFFF see Table 14 1 0x0C Reserved 0x10 Output Enable Register PIO_OER Write only 0x14 Output Disable Register PIO_ODR Write only 0x18 Output Status Register PIO_OSR Read only 0 0x1C Res...

Page 96: ...Access Type Write only Offset 0x04 This register is used to disable PIO control of individual pins When the PIO control is disabled the normal peripheral func tion is enabled on the corresponding pin...

Page 97: ...Write only Offset 0x10 This register is used to enable PIO output drivers If the pin is driven by a peripheral this has no effect on the pin but the information is stored The register is programmed a...

Page 98: ...register shows the PIO pin control output enable status which is programmed in PIO_OER and PIO ODR The defined value is effective only if the pin is controlled by the PIO The register reads as follow...

Page 99: ...e only Offset 0x24 This register is used to disable input glitch filters It affects the pin whether or not the PIO is enabled The register is pro grammed as follows 1 Disables the glitch filter on the...

Page 100: ...ccess Type Write only Offset 0x30 This register is used to set PIO output data It affects the pin only if the corresponding PIO output line is enabled and if the pin is controlled by the PIO Otherwise...

Page 101: ...hows the output data status which is programmed in PIO_SODR or PIO_CODR The defined value is effec tive only if the pin is controlled by the PIO Controller and only if the pin is defined as an output...

Page 102: ...er Register Name PIO_IER Access Type Write only Offset 0x40 This register is used to enable PIO interrupts on the corresponding pin It has effect whether PIO is enabled or not 1 Enables an interrupt w...

Page 103: ...t 0x48 This register shows which pins have interrupts enabled It is updated when interrupts are enabled or disabled by writing to PIO_IER or PIO_IDR 1 Interrupt is enabled on the corresponding input p...

Page 104: ...the pin or not and whether the pin is an input or output The register is reset to zero following a read and at reset 1 At least one change has been detected on the corresponding pin since the registe...

Page 105: ...dog timer has a 16 bit down counter Bits 12 15 of the value loaded when the watch dog is restarted are programmable using the HPVC parameter in WD_CMR Clock Mode Four clock sources are available to th...

Page 106: ...1 Disable the Watchdog by clearing the bit WDEN Write 0x2340 to WD_OMR This step is unnecessary if the WD is already disabled reset state 2 Initialize the WD Clock Mode Register Write 0x373C to WD_CM...

Page 107: ...ase Address 0xFFFF8000 Code Label WD_BASE Table 15 1 WD Memory Map Offset Register Name Access Reset State 0x00 Overflow Mode Register WD_OMR Read Write 0 0x04 Clock Mode Register WD_CMR Read Write 0...

Page 108: ...reset IRQEN Interrupt Enable Code Label WD_IRQEN 0 Generation of an interrupt by the Watch Dog is disabled 1 When overflow occurs the Watch Dog generates an interrupt EXTEN External Signal Enable Cod...

Page 109: ...1 set FFF and bits 12 to 15 equaling HPCV CKEY Clock Access Key Code Label WD_CKEY Used only when writing WD_CMR CKEY is read as 0 0x06E Write access in WD_CMR is allowed Other value Write access in W...

Page 110: ...gister Name WD_SR Access Read only Reset Value 0 Offset 0x0C WDOVF Watchdog Overflow Code Label WD_WDOVF 0 No watchdog overflow 1 A watchdog overflow has occurred since the last restart of the watchdo...

Page 111: ...special functions Chip identification RESET status Protect Mode see Section 13 10 Protect Mode on page 78 16 1 Chip Identification Table 16 1 provides the Chip ID values for the products as listed Tab...

Page 112: ...E Table 16 2 SF Memory Map Offset Register Name Access Reset State 0x00 Chip ID Register SF_CIDR Read only Hardwired 0x04 Chip ID Extension Register SF_EXID Read only Hardwired 0x08 Reset Status Regis...

Page 113: ...NVPSIZ Non Volatile Program Memory Size NVDSIZ Non Volatile Data Memory Size 31 30 29 28 27 26 25 24 EXT NVPTYP ARCH 23 22 21 20 19 18 17 16 ARCH VDSIZ 15 14 13 12 11 10 9 8 NVDSIZ NVPSIZ 7 6 5 4 3 2...

Page 114: ...ngle register definition without extensions 1 An extended Chip ID exists to be defined in the future VDSIZ Size Code Label SF_VDSIZ 0 0 0 0 None SF_VDSIZ_NONE 0 0 0 1 1K bytes SF_VDSIZ_1K 0 0 1 0 2K b...

Page 115: ...Status Register Register Name SF_RSR Access Type Read only Reset Value See Below Offset 0x08 RESET Reset Status Information This field indicates whether the reset was demanded by the external system v...

Page 116: ...ting SF_PMR PMRKEY is reads 0 0x27A8 Write access in SF_PMR is allowed Other value Write access in SF_PMR is prohibited AIC AIC Protect Mode Enable Code Label SF_AIC 0 The Advanced Interrupt Controlle...

Page 117: ...and Overrun Error Detection Line Break Generation and Detection Automatic Echo Local Loopback and Remote Loopback channel modes Multi drop Mode Address Detection and Generation Interrupt Generation T...

Page 118: ...Controller before enabling the transmitter or receiver 2 If the user selects one of the internal clocks SCK can be configured as a PIO Table 17 1 Name Description SCK USART Serial clock can be config...

Page 119: ...0 in the Mode Register US_MR the selected clock is divided by 16 times the value CD written in US_BRGR Baud Rate Generator Register If US_BRGR is set to 0 the Baud Rate Clock is disabled When the USAR...

Page 120: ...It is assumed that each bit lasts 16 cycles of the sampling clock one bit period so the sampling point is 8 cycles 0 5 bit periods after the start of the bit The first sampling point is therefore 24 c...

Page 121: ...t one data bit at high level a framing error is generated This sets FRAME in US_CSR 17 4 6 Time out This function allows an idle condition on the RXD line to be detected The maximum delay for which th...

Page 122: ...e idle state is programmed in US_TTGR Transmitter Time guard When this register is set to zero no time guard is generated Otherwise the transmitter holds a high level on TXD after each transmitted byt...

Page 123: ...Register is empty any previous character is fully transmitted TXEMPTY is cleared in US_CSR The break blocks the transmitter shift register until it is completed high level for at least 12 bit periods...

Page 124: ...ceive Break The receiver detects a break condition when all data parity and stop bits are low When the low stop bit is detected the receiver asserts the RXBRK bit in US_CSR An end of receive break is...

Page 125: ...er registers US_TCR and US_RCR are used to store the size of these buffers The receiver data transfer is triggered by the RXRDY bit and the transmitter data transfer is trig gered by TXRDY When a tran...

Page 126: ...received TXD and RXD pins are not used and the output of the transmitter is internally connected to the input of the receiver The RXD pin level has no effect and the TXD pin is held high as in idle s...

Page 127: ...ister US_IDR Write only 0x10 Interrupt Mask Register US_IMR Read only 0 0x14 Channel Status Register US_CSR Read only 0x18 0x18 Receiver Holding Register US_RHR Read only 0 0x1C Transmitter Holding Re...

Page 128: ...TXEN Transmitter Enable Code Label US_TXEN 0 No effect 1 The transmitter is enabled if TXDIS is 0 TXDIS Transmitter Disable Code Label US_TXDIS 0 No effect 1 The transmitter is disabled RSTSTA Reset...

Page 129: ...ak after a minimum of one character length and transmit a high level during 12 bit periods STTTO Start Time out Code Label US_STTTO 0 No effect 1 Start waiting for a character before clocking the time...

Page 130: ...us Mode Select Code Label US_SYNC 0 USART operates in Asynchronous Mode 1 USART operates in Synchronous Mode 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CLKO MODE9 15 14 13 12 11 10 9 8 CHMODE NBS...

Page 131: ...S_PAR_SPACE 0 1 1 Parity forced to 1 Mark US_PAR_MARK 1 0 x No parity US_PAR_NO 1 1 x Multi drop mode US_PAR_MULTIDROP NBSTOP Asynchronous SYNC 0 Synchronous SYNC 1 Code Label US_NBSTOP 0 0 1 stop bit...

Page 132: ...sfer Interrupt Code Label US_ENDRX 0 No effect 1 Enables End of Receive Transfer Interrupt ENDTX Enable End of Transmit Interrupt Code Label US_ENDTX 0 No effect 1 Enables End of Transmit Interrupt OV...

Page 133: ...AT91FR40162S Preliminary TIMEOUT Enable Time out Interrupt Code Label US_TIMEOUT 0 No effect 1 Enables Reception Time out Interrupt TXEMPTY Enable TXEMPTY Interrupt Code Label US_TXEMPTY 0 No effect 1...

Page 134: ...sfer Interrupt Code Label US_ENDRX 0 No effect 1 Disables End of Receive Transfer Interrupt ENDTX Disable End of Transmit Interrupt Code Label US_ENDTX 0 No effect 1 Disables End of Transmit Interrupt...

Page 135: ...91FR40162S Preliminary TIMEOUT Disable Time out Interrupt Code Label US_TIMEOUT 0 No effect 1 Disables Receiver Time out Interrupt TXEMPTY Disable TXEMPTY Interrupt Code Label US_TXEMPTY 0 No effect 1...

Page 136: ...End of Receive Transfer Interrupt is Disabled 1 End of Receive Transfer Interrupt is Enabled ENDTX Mask End of Transmit Interrupt Code Label US_ENDTX 0 End of Transmit Interrupt is Disabled 1 End of...

Page 137: ...TIMEOUT Mask Time out Interrupt Code Label US_TIMEOUT 0 Receive Time out Interrupt is Disabled 1 Receive Time out Interrupt is Enabled TXEMPTY Mask TXEMPTY Interrupt Code Label US_TXEMPTY 0 TXEMPTY In...

Page 138: ...DRX End of Receiver Transfer Code Label US_ENDRX 0 The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive 1 The End of Transfer signal from the Pe...

Page 139: ...t Time out command TXEMPTY Transmitter Empty Code Label US_TXEMPTY 0 There are characters in either US_THR or the Transmit Shift Register or a Break is being transmitted 1 There are no characters in U...

Page 140: ...ss Type Write only Offset 0x1C TXCHR Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set When number of data bits is less than 8 bits the bits...

Page 141: ...l clock Notes 1 Clock divisor bypass CD 1 must not be used when internal clock MCK is selected USCLKS 0 2 In Synchronous Mode the value programmed must be even to ensure a 50 50 mark space ratio 31 30...

Page 142: ...n to this register a Start Time out Command is automatically performed Time out duration TO x 4 x Bit period 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TO TO...

Page 143: ...Access Type Read Write Reset Value 0 Offset 0x30 RXPTR Receive Pointer RXPTR must be loaded with the address of the receive buffer 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9...

Page 144: ...d to the receiver 1 65535 Start Peripheral Data transfer if RXRDY is active 17 10 14 USART Transmit Pointer Register Name US_TPR Access Type Read Write Reset Value 0 Offset 0x38 TXPTR Transmit Pointer...

Page 145: ...e Reset Value 0 Offset 0x3C TXCTR Transmit Counter TXCTR must be loaded with the size of the transmit buffer 0 Stop Peripheral Data Transfer dedicated to the transmitter 1 65535 Start Peripheral Data...

Page 146: ...nter channel has 3 external clock inputs 5 internal clock inputs and 2 multi pur pose input output signals which can be configured by the user Each channel drives an internal interrupt signal which ca...

Page 147: ...Controller TC1XC1S TC0XC0S TC2XC2S INT INT INT TIOA0 TIOA1 TIOA2 TIOB0 TIOB1 TIOB2 XC0 XC1 XC2 XC0 XC1 XC2 XC0 XC1 XC2 TCLK0 TCLK1 TCLK2 TCLK0 TCLK1 TCLK2 TCLK0 TCLK1 TCLK2 TIOA1 TIOA2 TIOA0 TIOA2 TIO...

Page 148: ...x0000 an overflow occurs and the bit COVFS in TC_SR Status Register is set The current value of the counter is accessible in real time by reading TC_CV The counter can be reset by a trigger In this ca...

Page 149: ...4 External clock signals XC0 XC1 or XC2 The selected clock can be inverted with the CLKI bit in TC_CMR Channel Mode This allows counting on the opposite edges of the clock The burst function allows th...

Page 150: ...pped by an RB load event in Capture Mode LDBSTOP 1 in TC_CMR or a RC compare event in Waveform Mode CPCSTOP 1 in TC_CMR The start and the stop commands have effect only if the clock is enabled Figure...

Page 151: ...mer Counter channel can also be configured to have an external trigger In Capture Mode the external trigger signal can be selected between TIOA and TIOB In Waveform Mode an external event can be progr...

Page 152: ...s overwritten 18 4 2 Trigger Conditions In addition to the SYNC signal the software trigger and the RC compare trigger an external trig ger can be defined Bit ABETRG in TC_CMR selects input signal TIO...

Page 153: ...N CLKDIS BURST TIOB Register C Capture Register A Capture Register B Compare RC 16 bit Counter ABETRG SWTRG ETRGEDG CPCTRG TC_IMR Trig LDRBS LDRAS ETRGS TC_SR LOVRS COVFS SYNC 1 MTIOB TIOA MTIOA LDRA...

Page 154: ...sets the counter so RC can control the period of PWM waveforms External Event Trigger Conditions An external event can be programmed to be detected on one of the clock sources XC0 XC1 XC2 or TIOB The...

Page 155: ...s There has been a RB Compare match at least once since the last read of the status CPCS RC Compare Status There has been a RC Compare match at least once since the last read of the status COVFS Count...

Page 156: ...EN CLKDIS CPCDIS BURST TIOB Register A Register B Register C Compare RA Compare RB Compare RC CPCSTOP 16 bit Counter EEVT EEVTEDG SYNC SWTRG ENETRG CPCTRG TC_IMR Trig ACPC ACPA AEEVT ASWTRG BCPC BCPB...

Page 157: ...TC Channel 0 See Table 18 3 0x40 TC Channel 1 See Table 18 3 0x80 TC Channel 2 See Table 18 3 0xC0 TC Block Control Register TC_BCR Write only 0xC4 TC Block Mode Register TC_BMR Read Write 0 Table 18...

Page 158: ...r Register Name TC_BCR Access Type Write only Offset 0xC0 SYNC Synchro Command 0 No effect 1 Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels 31 30 29...

Page 159: ...External Clock Signal 1 Selection TC2XC2S External Clock Signal 2 Selection 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TC2XC2S TC1XC1S TC0XC0S TC0XC0S Signa...

Page 160: ...CLKEN 0 No effect 1 Enables the clock if CLKDIS is not 1 CLKDIS Counter Clock Disable Command Code Label TC_CLKDIS 0 No effect 1 Disables the clock SWTRG Software Trigger Command Code Label TC_SWTRG 0...

Page 161: ...LDRA 15 14 13 12 11 10 9 8 WAVE 0 CPCTRG ABETRG ETRGEDG 7 6 5 4 3 2 1 0 LDBDIS LDBSTOP BURST CLKI TCCLKS TCCLKS Clock Selected Code Label TC_CLKS 0 0 0 MCK 2 TC_CLKS_MCK2 0 0 1 MCK 8 TC_CLKS_MCK8 0 1...

Page 162: ...has no effect on the counter and its clock 1 RC Compare resets the counter and starts the counter clock WAVE 0 Code Label TC_WAVE 0 Capture Mode is enabled 1 Capture Mode is disabled Waveform Mode is...

Page 163: ...R40162S Preliminary LDRB RB Loading Selection LDRB Edge Code Label TC_LDRB 0 0 None TC_LDRB_EDGE_NONE 0 1 Rising edge of TIOA TC_LDRB_RISING_EDGE 1 0 Falling edge of TIOA TC_LDRB_FALLING_EDGE 1 1 Each...

Page 164: ...WTRG AEEVT ACPC ACPA 15 14 13 12 11 10 9 8 WAVE 1 CPCTRG ENETRG EEVT EEVTEDG 7 6 5 4 3 2 1 0 CPCDIS CPCSTOP BURST CLKI TCCLKS TCCLKS Clock Selected Code Label TC_CLKS 0 0 0 MCK 2 TC_CLKS_MCK2 0 0 1 MC...

Page 165: ...The external event has no effect on the counter and its clock In this case the selected external event only controls the TIOA output 1 The external event resets the counter and starts the counter cloc...

Page 166: ...1 1 Toggle TC_ACPA_TOGGLE_OUTPUT ACPC Effect Code Label TC_ACPC 0 0 None TC_ACPC_OUTPUT_NONE 0 1 Set TC_ACPC_SET_OUTPUT 1 0 Clear TC_ACPC_CLEAR_OUTPUT 1 1 Toggle TC_ACPC_TOGGLE_OUTPUT AEEVT Effect Co...

Page 167: ...1 1 Toggle TC_BCPB_TOGGLE_OUTPUT BCPC Effect Code Label TC_BCPC 0 0 None TC_BCPC_OUTPUT_NONE 0 1 Set TC_BCPC_SET_OUTPUT 1 0 Clear TC_BCPC_CLEAR_OUTPUT 1 1 Toggle TC_BCPC_TOGGLE_OUTPUT BEEVT Effect Co...

Page 168: ...unter value in real time 18 6 7 TC Register A Register Name TC_RA Access Type Read only if WAVE 0 Read Write if WAVE 1 Reset Value 0 Offset 0x14 RA Register A Code Label TC_RA RA contains the Register...

Page 169: ...RB RB contains the Register B value in real time 18 6 9 TC Register C Register Name TC_RC Access Type Read Write Reset Value 0 Offset 0x1C RC Register C Code Label TC_RC RC contains the Register C val...

Page 170: ...as not occurred since the last read of the Status Register or WAVE 0 1 RB Compare has occurred since the last read of the Status Register if WAVE 1 CPCS RC Compare Status Code Label TC_CPCS 0 RC Compa...

Page 171: ...that TIOA pin is low If WAVE 1 this means that TIOA is driven low 1 TIOA is high If WAVE 0 this means that TIOA pin is high If WAVE 1 this means that TIOA is driven high MTIOB TIOB Mirror Code Label T...

Page 172: ...les the RA Compare Interrupt CPBS RB Compare Code Label TC_CPBS 0 No effect 1 Enables the RB Compare Interrupt CPCS RC Compare Code Label TC_CPCS 0 No effect 1 Enables the RC Compare Interrupt LDRAS R...

Page 173: ...re Interrupt if WAVE 1 CPBS RB Compare Code Label TC_CPBS 0 No effect 1 Disables the RB Compare Interrupt if WAVE 1 CPCS RC Compare Code Label TC_CPCS 0 No effect 1 Disables the RC Compare Interrupt L...

Page 174: ...enabled CPBS RB Compare Code Label TC_CPBS 0 The RB Compare Interrupt is disabled 1 The RB Compare Interrupt is enabled CPCS RC Compare Code Label TC_CPCS 0 The RC Compare Interrupt is disabled 1 The...

Page 175: ...a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied Exposure to absolute m...

Page 176: ...nits VDDIO DC Supply I Os 2 7 3 6 V VDDCORE DC Supply Core 1 65 1 95 V VIL Input Low Voltage 0 3 0 8 V VIH Input High Voltage 2 0 VDDIO 0 3 V VOL Output Low Voltage Pin Group 1 2 IOL 16 mA 1 0 4 V Pin...

Page 177: ...andby Current CMOS CE VCC 0 3V to VCC 13 25 A ICC 1 VCC Active Read Current f 5 MHz IOUT 0 mA 12 25 mA ICC1 VCC Programming Current 40 mA IPP1 VPP Input Load Current 5 A VIL Input Low Voltage 0 6 V VI...

Page 178: ...mW MHz Normal Fetch in ARM mode from internal SRAM All peripheral clocks activated 0 83 Fetch in ARM mode from internal SRAM All peripheral clocks deactivated 0 73 Fetch in ARM mode from external SRAM...

Page 179: ...tCL Low Half period 5 5 ns Table 19 8 Clock Propagation Times Symbol Parameter Conditions Min Max Units tCDLH Rising Edge Propagation Time CMCKO 0 pF 4 4 6 6 ns CMCKO derating 0 199 0 295 ns pF tCDHL...

Page 180: ...180 6174B ATARM 07 Nov 05 AT91FR40162S Preliminary Figure 19 2 MCKO Relative to NRST NRST tD MCKO...

Page 181: ...ons the following equation should be used Where T is the derating factor in temperature given in Figure 20 1 on page 182 VDDCORE is the derating factor for the Core Power Supply given in Figure 20 2 o...

Page 182: ...e Derating Factor Figure 20 2 Core Voltage Derating Factor 0 8 0 9 1 1 1 1 2 60 40 20 0 20 40 60 80 100 120 140 160 Operating Temperature C Derating Factor Derating Factor for Typ Case is 1 0 5 1 1 5...

Page 183: ...minary 20 1 4 IO Voltage Derating Factor Figure 20 3 Derating Factor for Different VDDIO Power Supply Levels 0 8 0 9 1 1 1 1 2 1 3 1 4 1 5 1 6 2 2 2 2 4 2 6 2 8 3 3 2 3 4 3 6 VDDIO Voltage Level Derat...

Page 184: ...l count Detection mode The inputs have to meet the minimum pulse width and minimum input period shown in Table 20 3 and Table 20 4 and as represented in Figure 20 5 Table 20 1 USART Input Minimum Puls...

Page 185: ...ve to meet the minimum pulse width and minimum input period shown in Table 20 6 and Table 20 7 and represented in Figure 20 7 MCKI TIOA TIOB TCLK TC1 3 tCP 2 3 tCP 2 TC2 Table 20 5 Reset Minimum Pulse...

Page 186: ...IO1 PIO Input Minimum Pulse Width 3 tCP 2 ns PIO Inputs PIO1 Table 20 9 ICE Interface Timing Specifications Symbol Parameter Conditions Min Max Units ICE0 NTRST Minimum Pulse Width 10 9 ns ICE1 NTRST...

Page 187: ...187 6174B ATARM 07 Nov 05 AT91FR40162S Preliminary Figure 20 9 ICE Interface Signal TCK ICE3 ICE4 ICE7 ICE6 ICE9 ICE8 TMS TDI TDO ICE0 ICE5 NTRST ICE1 ICE2...

Page 188: ...CKI Rising 1 7 ns Table 20 11 EBI Write Signals Symbol Parameter Conditions Min Max Units EBI7 MCKI Rising to NWR Active No Wait States CNWR 0 pF 3 9 6 3 ns CNWR derating 0 029 0 043 ns pF EBI8 MCKI R...

Page 189: ...Signals Continued Symbol Parameter Conditions Min Max Units Table 20 12 EBI Read Signals Symbol Parameter Conditions Min Max Units EBI21 MCKI Falling to NRD Active 1 CNRD 0 pF 4 5 7 9 ns CNRD deratin...

Page 190: ...elect programmed with 0 wait state If this condition is not met at least one wait state must be programmed EBI31 Data Setup before NRD High 5 CNRD 0 pF 8 0 ns CNRD derating 0 044 ns pF EBI32 Data Hold...

Page 191: ...tandard Read Protocol NCS A1 A23 NRD 1 D0 D15 Read MCKI NUB NLB A0 NRD 2 NWAIT NWR No Wait States D0 D15 to Write NWR Wait States No Wait Wait EBI1 EBI2 EBI3 EBI4 EBI5 EBI6 EBI7 EBI9 EBI8 EBI10 EBI11...

Page 192: ...hout impact on tACC 3 tDF is specified from OE or CE whichever occurs first CL 5 pF 4 This parameter is characterized and is not 100 tested Table 20 14 AC Flash Read Characteristics Symbol Parameter M...

Page 193: ...12 Input Test Waveforms and Measurement Level tR tF 5 ns 20 4 3 Output Test Load Figure 20 13 Output Test Load 20 4 4 Pin Capacitance Note 1 This parameter is characterized and is not 100 tested Table...

Page 194: ...olled Table 20 16 AC Byte Word Load Waveforms Symbol Parameter Min Max Units tAS tOES Address OE Setup Time 0 ns tAH Address Hold Time 35 ns tCS Chip Select Setup Time 0 ns tCH Chip Select Hold Time 0...

Page 195: ...195 6174B ATARM 07 Nov 05 AT91FR40162S Preliminary 20 5 2 CE Controlled Figure 20 15 CE Controlled...

Page 196: ...ss Setup Time 0 ns tAH Address Hold Time 35 ns tDS Data Setup Time 35 ns tDH Data Hold Time 0 ns tWP Write Pulse Width 35 ns tWPH Write Pulse Width High 35 ns tWC Write Cycle Time 70 ns tRP Reset Puls...

Page 197: ...For chip erase the address should be 555 For sector erase the address depends on what sector is to be erased See footnote 3 of Table 11 2 Command Definition Table on page 61 3 For chip erase the data...

Page 198: ...spec in AC Flash Read Characteristics on page 192 20 7 1 Data Polling Waveforms Figure 20 18 Data Polling Waveforms Table 20 18 Data Polling Characterisitics 1 Symbol Parameter Min Typ Max Units tDH...

Page 199: ...orms 1 2 3 Notes 1 Toggling either OE or CE or both OE and CE will operate toggle bit The tOEHP specification must be met by the toggling input s 2 Beginning and ending state of I O6 will vary 3 Any a...

Page 200: ...SINK cooling device thermal resistance C W provided in the device datasheet PD device power consumption W estimated from data provided in Section 19 5 Power Consumption on page 178 TA ambient tempera...

Page 201: ...Junction to ambient thermal resistance Still Air 121 BGA 6 C W JC Junction to case thermal resistance 121 BGA 7 3 Table 21 2 Device and 121 ball BGA Package Maximum Weight 194 mg Table 21 3 121 ball...

Page 202: ...three reflow passes is allowed per component Table 21 4 Package Reference JESD97 Classification e1 Table 21 5 Soldering Profile RoHS Compliant Package Profile Feature Convection or IR Convection Aver...

Page 203: ...TARM 07 Nov 05 AT91FR40162S Preliminary 22 Ordering Information Table 22 1 Ordering Information Ordering Code Package Package Type Temperature Operating Range AT91FR40162S CJ BGA 121 RoHS Industrial 4...

Page 204: ...204 6174B ATARM 07 Nov 05 AT91FR40162S Preliminary 23 AT91FR40162S Errata There is no known errata for the AT91FR40162S...

Page 205: ...4 Reset 8 6 5 Emulation Functions 9 6 6 Memory Controller 10 6 7 AT91 Flash Memory Uploader FMU Software 13 7 Peripherals 15 7 1 System Peripherals 16 7 2 User Peripherals 17 8 Memory Map 18 9 Periphe...

Page 206: ...11 11 Common Flash Interface Definition 66 12 PS Power saving 68 12 1 Peripheral Clocks 68 12 2 Power Saving PS User Interface 69 13 AIC Advanced Interrupt Controller 74 13 1 Block Diagram 74 13 2 Har...

Page 207: ...tion 118 17 3 Baud Rate Generator 119 17 4 Receiver 120 17 5 Transmitter 122 17 6 Break 123 17 7 Peripheral Data Controller 125 17 8 Interrupt Generation 125 17 9 Channel Modes 126 17 10 USART User In...

Page 208: ...AC Flash Read Characteristics 192 20 5 AC Flash Byte Word Load Waveforms 194 20 6 Flash Program Cycle Characteristics 196 20 7 Flash Data Polling Characteristics 198 20 8 Flash Toggle Bit Characteris...

Page 209: ...omments Change Request Ref 6174A 20 Jun 05 First issue Qualified on the Intranet published on the web 6174B 07 Nov 05 note removed Table 19 7 on page 179 Changes to Table 19 2 on page 176 and Table 21...

Page 210: ...rsenaux 41 Case Postale 80 CH 1705 Fribourg Switzerland Tel 41 26 426 5555 Fax 41 26 426 5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel 852 2721 9778 Fa...

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