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6174B–ATARM–07-Nov-05
AT91FR40162S Preliminary
Figure 17-5. Synchronous Mode: Character Reception
17.4.3
Receiver Ready
When a complete character is received, it is transferred to the US_RHR and the RXRDY status
bit in US_CSR is set. If US_RHR has not been read since the last transfer, the OVRE status bit
in US_CSR is set.
17.4.4
Parity Error
Each time a character is received, the receiver calculates the parity of the received data bits, in
accordance with the field PAR in US_MR. It then compares the result with the received parity bit.
If different, the parity error bit PARE in US_CSR is set.
17.4.5
Framing Error
If a character is received with a stop bit at low level and with at least one data bit at high level, a
framing error is generated. This sets FRAME in US_CSR.
17.4.6
Time-out
This function allows an idle condition on the RXD line to be detected. The maximum delay for
which the USART should wait for a new character to arrive while the RXD line is inactive (high
level) is programmed in US_RTOR (Receiver Time-out). When this register is set to 0, no time-
out is detected. Otherwise, the receiver waits for a first character and then initializes a counter
which is decremented at each bit period and reloaded at each byte reception. When the counter
reaches 0, the TIMEOUT bit in US_CSR is set. The user can restart the wait for a first character
with the STTTO (Start Time-out) bit in US_CR.
Calculation of time-out duration:
D0
D1
D2
D3
D4
D5
D6
D7
RXD
True Start Detection
Sampling
Parity Bit
Stop Bit
Example: 8-bit, parity enabled 1 stop
SCK
Duration
=
Value x
4
x
Bit period
