68
6174B–ATARM–07-Nov-05
AT91FR40162S Preliminary
12. PS: Power-saving
The AT91X40 Series’ Power-saving feature enables optimization of power consumption. The PS
controls the CPU and Peripheral Clocks. One control register (PS_CR) enables the user to stop
the ARM7TDMI Clock and enter Idle Mode. One set of registers with a set/clear mechanism
enables and disables the peripheral clocks individually.
The ARM7TDMI clock is enabled after a reset and is automatically re-enabled by any enabled
interrupt in the Idle Mode.
12.1
Peripheral Clocks
The clock of each peripheral integrated in the AT91FR40162S can be individually enabled and
disabled by writing to the Peripheral Clock Enable (PS_PCER) and Peripheral Clock Disable
Registers (PS_PCDR). The status of the peripheral clocks can be read in the Peripheral Clock
Status Register (PS_PCSR).
When a peripheral clock is disabled, the clock is immediately stopped. When the clock is re-
enabled, the peripheral resumes action where it left off.
To avoid data corruption or erroneous behavior of the system, the system software only disables
the clock after all programmed peripheral operations have finished.
The peripheral clocks are automatically enabled after a reset.
The bits that control the peripheral clocks are the same as those that control the Interrupt
Sources in the AIC.
