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6174B–ATARM–07-Nov-05
AT91FR40162S Preliminary
programmed to be level sensitive, the source of the interrupt must be cleared during
this phase.
7.
The I bit in the CPSR must be set in order to mask interrupts before exiting, to ensure
that the interrupt is completed in an orderly manner.
8.
The End Of Interrupt Command Register (AIC_EOICR) must be written in order to indi-
cate to the AIC that the current interrupt is finished. This causes the current level to be
popped from the stack, restoring the previous current level if one exists on the stack. If
another interrupt is pending, with lower or equal priority than old current level but with
higher priority than the new current level, the NIRQ line is re-asserted, but the interrupt
sequence does not immediately start because the I bit is set in the core.
9.
The SPSR (SPSR_irq) is restored. Finally, the saved value of the Link Register is
restored directly into the PC. This has effect of returning from the interrupt to whatever
was being executed before, and of loading the CPSR with the stored SPSR, masking or
unmasking the interrupts depending on the state saved in the SPSR (the previous state
of the ARM core).
Note:
The I bit in the SPSR is significant. If it is set, it indicates that the ARM core was just about to mask
IRQ interrupts when the mask instruction was interrupted. Hence, when the SPSR is restored, the
mask instruction is completed (IRQ is masked).
13.12 Fast Interrupt Sequence
It is assumed that:
• The Advanced Interrupt Controller has been programmed, AIC_SVR[0] is loaded with fast
interrupt service routine address and the fast interrupt is enabled.
• The Instruction at address 0x1C(FIQ exception vector address) is:
• ldr pc, [pc, # - &F20].
• Nested Fast Interrupts are not needed by the user.
When NFIQ is asserted, if the bit F of CPSR is 0, the sequence is:
1.
The CPSR is stored in SPSR_fiq, the current value of the Program Counter is loaded in
the FIQ link register (r14_fiq) and the Program Counter (r15) is loaded with 0x1C. In the
following cycle, during fetch at address 0x20, the ARM core adjusts r14_fiq, decrement-
ing it by 4.
2.
The ARM core enters FIQ Mode.
3.
When the instruction loaded at address 0x1C is executed, the Program Counter is
loaded with the value read in AIC_FVR. Reading the AIC_FVR has effect of automati-
cally clearing the fast interrupt (source 0 connected to the FIQ line), if it has been
programmed to be edge triggered. In this case only, it de-asserts the NFIQ line on the
processor.
4.
The previous step has effect to branch to the corresponding interrupt service routine. It
is not necessary to save the Link Register(r14_fiq) and the SPSR(SPSR_fiq) if nested
fast interrupts are not needed.
5.
The Interrupt Handler can then proceed as required. It is not necessary to save regis-
ters r8 to r13 because FIQ Mode has its own dedicated registers and the user r8 to r13
are banked. The other registers, r0 to r7, must be saved before being used, and
restored at the end (before the next step). Note that if the fast interrupt is programmed
to be level sensitive, the source of the interrupt must be cleared during this phase in
order to de-assert the NFIQ line.
6.
Finally, the Link Register (r14_fiq) is restored into the PC after decrementing it by 4
(with instruction sub pc, lr, #4 for example). This has effect of returning from the inter-
