10
6174B–ATARM–07-Nov-05
AT91FR40162S Preliminary
6.6
Memory Controller
The ARM7TDMI processor address space is 4G bytes. The memory controller decodes the
internal 32-bit address bus and defines three address spaces:
• Internal memories in the four lowest megabytes
• Middle space reserved for the external devices (memory or peripherals) controlled by the EBI
• Internal peripherals in the four highest megabytes
In any of these address spaces, the ARM7TDMI operates in little-endian mode only.
6.6.1
Internal Memories
The AT91FR40162S microcontroller integrates 256K bytes of internal SRAM. It is 32 bits wide
and single-clock cycle accessible. Byte (8-bit), half-word (16-bit) and word (32-bit) accesses are
supported and are executed within one cycle. Fetching either Thumb or ARM instructions is sup-
ported, and internal memory can store two times as many Thumb instructions as ARM
instructions.
The SRAM is mapped at address 0x0 (after the Remap command), allowing ARM7TDMI excep-
tion vectors between 0x0 and 0x20 to be modified by the software.
Placing the SRAM on-chip and using the 32-bit data bus bandwidth maximizes the microcontrol-
ler performance and minimizes system power consumption. The 32-bit bus increases the
effectiveness of the use of the ARM instruction set and the processing of data that is wider than
16 bits, thus making optimal use of the ARM7TDMI advanced performance.
Being able to dynamically update application software in the 256-Kbyte SRAM adds an extra
dimension to the AT91FR40162S.
The AT91FR40162S also integrates a 2-Mbyte Flash memory that is accessed via the External
Bus Interface. All data, address and control lines, except for the Chip Select signal, are con-
nected within the device.
6.6.2
Boot Mode Select
The ARM reset vector is at address 0x0. After the NRST line is released, the ARM7TDMI exe-
cutes the instruction stored at this address. This means that this address must be mapped in
nonvolatile memory after the reset. The input level on the BMS pin during the last 10 clock
cycles before the rising edge of the NRST selects the type of boot memory (see
).
If the embedded Flash memory is to be used as boot memory, the BMS input must be pulled
down externally and NCS0 must be connected to NCSF externally.
The pin BMS is multiplexed with the I/O line P24 that can be programmed after reset like any
standard PIO line.
Table 6-1.
Boot Mode Select
BMS
Boot Memory
1
External 8-bit memory on NCS0
0
Internal or External 16-bit memory on NCS0
