Atmel AT91FR40162S, Manual

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6174B–ATARM–07-Nov-05
AT91FR40162S Preliminary
Figure 10-21 through Figure 10-27 show the timing cycles and wait states for read and write
access to the various AT91FR40162S external memory devices. The configurations described
are shown in the following table:
Table 10-3. Memory Access Waveforms
Figure Number Number of Wait States Bus Width Size of Data Transfer
Figure 10-21 0 16 Word
Figure 10-22 1 16 Word
Figure 10-23 1 16 Half-word
Figure 10-24 0 8 Word
Figure 10-25 1 8 Half-word
Figure 10-26 1 8 Byte
Figure 10-27 0 16 Byte