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6174B–ATARM–07-Nov-05
AT91FR40162S Preliminary
11.1
Block Diagram
Figure 11-1.
11.2
Device Operation
11.2.1
Read
The Flash Memory is accessed like an EPROM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the address pins are asserted on the outputs.
The outputs are put in the high impedance state whenever CE or OE is high. This dual-line con-
trol gives designers flexibility in preventing bus contention.
11.2.2
Command Sequences
When the device is first powered on, it will be reset to the read or standby mode, depending
upon the state of the control line inputs. In order to perform other device functions, a series of
command sequences are entered into the device. The command sequences are shown in the
”Command Definition Table” on page 61
(I/O8 - I/O15 are don’t care inputs for the command
codes). The command sequences are written by applying a low pulse on the WE or CE input
with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE
or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Standard
microprocessor write timings are used. The address locations used in the command sequences
are not affected by entering the command sequences.
Identifier
Register
Status
Register
Data
Comparator
Output
Multiplexor
Output
Buffer
Input
Buffer
Command
Register
Data
Register
Y-GATING
Write State
Machine
Program/Erase
Voltage Switch
CE
WE
OE
RESET
BYTE
RDY/BUSY
VPP
VCC
GND
Y-Decoder
X-Decoder
Input
Buffer
Address
Latch
I/O0 - I/O15/A-1
A0 - A19
Main Memory
