Atmel AT91FR40162S, Manual

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6174B–ATARM–07-Nov-05
AT91FR40162S Preliminary
Note: 1. Bit Number refers to the data bit that corresponds to this signal in each of the User Interface registers.
Table 14-1. Multiplexed Parallel I/Os
PIO Controller Peripheral
Reset State
Pin
Number
Bit
Number
(1)
Port Name Port Name Signal Description Signal Direction
0 P0 TCLK0 Timer 0 Clock signal Input PIO Input 49
1 P1 TIOA0 Timer 0 Signal A Bi-directional PIO Input 50
2 P2 TIOB0 Timer 0 Signal B Bi-directional PIO Input 51
3 P3 TCLK1 Timer 1 Clock signal Input PIO Input 54
4 P4 TIOA1 Timer 1 Signal A Bi-directional PIO Input 55
5 P5 TIOB1 Timer 1 Signal B Bi-directional PIO Input 56
6 P6 TCLK2 Timer 2 Clock signal Input PIO Input 57
7 P7 TIOA2 Timer 2 Signal A Bi-directional PIO Input 58
8 P8 TIOB2 Timer 2 Signal B Bi-directional PIO Input 59
9 P9 IRQ0 External Interrupt 0 Input PIO Input 60
10 P10 IRQ1 External Interrupt 1 Input PIO Input 63
11 P11 IRQ2 External Interrupt 2 Input PIO Input 64
12 P12 FIQ Fast Interrupt Input PIO Input 66
13 P13 SCK0 USART 0 clock signal Bi-directional PIO Input 67
14 P14 TXD0 USART 0 transmit data signal Output PIO Input 68
15 P15 RXD0 USART 0 receive data signal Input PIO Input 69
16 P16 – – – PIO Input 70
17 P17 – – – PIO Input 71
18 P18 – – – PIO Input 72
19 P19 – – – PIO Input 73
20 P20 SCK1 USART 1 clock signal Bi-directional PIO Input 74
21 P21 TXD1 USART 1 transmit data signal Output PIO Input 75
22 P22 RXD1 USART 1 receive data signal Input PIO Input 76
23 P23 – – – PIO Input 83
24 P24 – – – PIO Input 84
25 P25 MCKO Master Clock Output Output MCKO 85
26 P26 NCS2 Chip Select 2 Output NCS2 99
27 P27 NCS3 Chip Select 3 Output NCS3 100
28 P28 A20/CS7 Address 20/Chip Select 7 Output A20 25
29 P29 A21/CS6 Address 21/Chip Select 6 Output A21 26
30 P30 A22/CS5 Address 22/Chip Select 5 Output A22 29
31 P31 A23/CS4 Address 23/Chip Select 4 Output A23 30