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6174B–ATARM–07-Nov-05
AT91FR40162S Preliminary
7.1
System Peripherals
7.1.1
PS: Power-saving
The power-saving feature optimizes power consumption, enabling the software to stop the
ARM7TDMI clock (idle mode), restarting it when the module receives an interrupt (or reset). It
also enables on-chip peripheral clocks to be enabled and disabled individually, matching power
consumption and application needs.
7.1.2
AIC: Advanced Interrupt Controller
The Advanced Interrupt Controller has an 8-level priority, individually maskable, vectored inter-
rupt controller, and drives the NIRQ and NFIQ pins of the ARM7TDMI from:
• The external fast interrupt line (FIQ)
• The three external interrupt request lines (IRQ0 - IRQ2)
• The interrupt signals from the on-chip peripherals
The AIC is extensively programmable offering maximum flexibility, and its vectoring features
reduce the real-time overhead in handling interrupts.
The AIC also features a spurious vector detection feature, which reduces spurious interrupt han-
dling to a minimum, and a protect mode that facilitates the debug capabilities.
7.1.3
PIO: Parallel I/O Controller
The AT91FR40162S has 32 programmable I/O lines. Six pins are dedicated as general-purpose
I/O pins. Other I/O lines are multiplexed with an external signal of a peripheral to optimize the
use of available package pins. The PIO controller enables generation of an interrupt on input
change and insertion of a simple input glitch filter on any of the PIO pins.
7.1.4
WD: Watchdog
The Watchdog is built around a 16-bit counter and is used to prevent system lock-up if the soft-
ware becomes trapped in a deadlock. It can generate an internal reset or interrupt, or assert an
active level on the dedicated pin NWDOVF. All programming registers are password-protected
to prevent unintentional programming.
7.1.5
SF: Special Function
The AT91FR40162S provides registers that implement the following special functions.
• Chip Identification
• RESET Status
• Protect Mode
