Programmers Model
ARM DDI 0363G
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3-13
ID073015
Non-Confidential
3.6.11
The M bits
M[4:0] are the mode bits. These bits determine the processor operating mode as
shows.
Note
•
In Privileged mode an illegal value programmed into M[4:0] causes the processor to enter
System mode.
•
In User mode M[4:0] can be read. Writes to M[4:0] are ignored.
3.6.12
Modification of PSR bits by MSR instructions
In the ARMv7-R architecture each CPSR bit falls into one of these categories:
•
Bits that are freely modifiable from any mode, either directly by
MSR
instructions or by
other instructions whose side-effects include writing the specific bit or writing the entire
CPSR.
Bits in
that are in this category are N, Z, C, V, Q, GE[3:0], and E.
•
Bits that an
MSR
instruction must never modify, and so must only be written as a side-effect
of another instruction. If an
MSR
instruction tries to modify these bits, the results are
architecturally Unpredictable. In the processor these bits are not affected.
The bits in
that are in this category are the execution state bits
[26:24], [15:10], and [5].
•
Bits that can only be modified from Privileged modes, and that instructions completely
protect from modification while the processor is in User mode. Entering a processor
exception is the only way to modify these bits while the processor is in User mode, as
described in
that are in this category are A, I, F, and M[4:0].
Table 3-3 PSR mode bit values
M[4:0]
Mode
b10000
User
b10001
FIQ
b10010
IRQ
b10011
Supervisor
b10111
Abort
b11011
Undefined
b11111
System