Functional Description
ARM DDI 0363G
Copyright © 2006-2011 ARM Limited. All rights reserved.
2-5
ID073015
Non-Confidential
•
ECC code generation, single-bit error correction, and two-bit error detection.
Similarly, you can configure the TCM interfaces for:
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parity generation and error detection
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ECC code generation, single-bit error correction, and two-bit error detection.
For more information, see
.
2.1.5
L2 AXI interfaces
The L2 AXI interfaces enable the L1 memory system to have access to peripherals and to
external memory using an AXI master and AXI slave port.
AXI master interface
The AXI master interface provides a high bandwidth interface to second level caches, on-chip
RAM, peripherals, and interfaces to external memory. It consists of a single AXI port with a
64-bit read channel and a 64-bit write channel for instruction and data fetches.
The AXI master can run at the same frequency as the processor, or at a lower synchronous
frequency. If asynchronous clocking is required an external asynchronous AXI slice is required.
AXI slave interface
The AXI slave interface enables AXI masters, including the AXI master port of the processor,
to access data and instruction cache RAMs and TCMs through the AXI system bus. You can use
this for DMA into and out of the TCM RAMs and for software test of the cache RAMs.
The slave interface can run at the same frequency as the processor or at a lower, synchronous
frequency. If asynchronous clocking is required an external asynchronous AXI slice is required.
Bits in the Auxiliary Control Register and Slave Port Control Register can control access to the
AXI slave. Access to the TCM RAMs can be granted to any master, to only privileged masters,
or completely disabled. Access to the cache RAMs can be separately controlled in a similar way.
2.1.6
Debug
The processor has a CoreSight compliant
Advanced Peripheral Bus version 3
(APBv3) debug
interface. This permits system access to debug resources, for example, the setting of
watchpoints and breakpoints.
The processor provides extensive support for real-time debug and performance profiling.
The following sections give an overview of debug:
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•
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System performance monitoring
This is a group of counters that you can configure to monitor the operation of the processor and
memory system. For more information, see
ETM interface
The
Embedded Trace Macrocell
(ETM) interface enables you to connect an external ETM unit
to the processor for real-time code tracing of the core in an embedded system.