Programmers Model
ARM DDI 0363G
Copyright © 2006-2011 ARM Limited. All rights reserved.
3-12
ID073015
Non-Confidential
Note
GE
bit is 1 if A op B
≥
C, otherwise 0.
The
SEL
instruction uses GE[3:0] to select which source register supplies each byte of its result.
See the
ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition
for more
information.
3.6.7
The E bit
ARM and Thumb instructions are provided to set and clear the E bit. The E bit controls
load/store endianness. See the
ARM Architecture Reference Manual
for information on where
the E bit is used.
3.6.8
The A bit
The A bit is set automatically by certain exceptions and is written by privileged software. It
disables asynchronous Data Aborts. For more information on how to use the A bit, see
.
3.6.9
The I and F bits
The I and F bits are the interrupt disable bits:
•
when the I bit is set, IRQ interrupts are disabled
•
when the F bit is set, FIQ interrupts are disabled.
Software can use
MSR
,
CPS
,
MOVS pc
,
SUBS pc
,
LDM ..,{..pc}^
, or
RFE
instructions to change the
values of the I and F bits. They are also set automatically by some exceptions.
When NMFIs are enabled, updates to the F bit are restricted. For more information see
.
3.6.10
The T bit
The T bit reflects the instruction set state:
•
when the T bit is set, the processor executes in Thumb state
•
when the T bit is clear, the processor executes in ARM state.
Note
Never use an
MSR
instruction to force a change to the state of the T bit in the CPSR. The processor
ignores any attempt to modify the T bit using an
MSR
instruction.