Events and Performance Monitor
ARM DDI 0363G
Copyright © 2006-2011 ARM Limited. All rights reserved.
6-13
ID073015
Non-Confidential
6.3.6
c9, Performance Counter Selection Register
The PMSELR Register characteristics are:
Purpose
•
selects an Event Count Register.
•
determines which count register is accessed or controlled by
accesses to the Event Type Selection Register and the Event Count
Register.
Usage constraints
The PMSELR Register is:
•
A read/write register.
•
Accessible in:
—
Privileged mode
—
User mode only when the PMUSERENR.EN bit is set to 1,
see
.
Configurations
Available in all processor configurations.
Attributes
shows the PMSELR bit assignments.
Figure 6-6 PMSELR Register bit assignments
shows the PMSELR bit assignments.
Any values programmed in the PMSELR Register other than those specified in
are
Unpredictable.
To access the PMSELR Register, write CP15 with:
MCR p15, 0, <Rd>, c9, c12, 5 ; Write PMSELR Register
6.3.7
c9, Cycle Count Register
The PMCCNTR Register characteristics are:
Purpose
Counts clock cycles.
Usage constraints
The PMCCNTR Register:
•
Is a 32-bit read/write register.
SEL
31
4
0
Reserved
5
Table 6-7 PMSELR Register bit assignments
Bits
Name
Function
[31:5]
-
RAZ on reads, SBZP on writes
[4:0]
SEL
Counter select:
b00000 = selects counter 0
b00001 = selects counter 1
b00010 = selects counter 2.