ARM Cortex-R4 Technical Reference Manual Download Page 384

Page: 384 / 436

AC Characteristics

ARM DDI 0363G

B-3

ID073015

Non-Confidential

B.2

Processor timing parameters

This section describes the input and output port timing parameters for the processor.

The maximum timing parameter or constraint delay for each processor signal applied to the SoC
is given as a percentage in

Table B-1

Table B-17 on page B-11

. The input and output delay

columns provide the maximum and minimum time as a percentage of the processor clock cycle
given to the SoC for that signal.

This section describes:
•

Input port timing parameters

•

Output ports timing parameters

on page B-8

B.2.1

Input port timing parameters

Table B-1

shows the timing parameters for the miscellaneous input ports.

Table B-2

shows the timing parameters for the configuration input port.

Table B-1 Miscellaneous input ports timing parameters:

Input delay
minimum

Input delay
maximum

Signal name

Clock uncertainty

10%

nRESET

Clock uncertainty

10%

nSYSPORESET

Clock uncertainty

10%

PRESETDBGn

Clock uncertainty

50%

nCPUHALT

Clock uncertainty

20%

DBGNOCLKSTOP

Table B-2 Configuration input port timing parameters

Input delay
minimum

Input delay
maximum

Signal name

Clock uncertainty

20%

VINITHI

Clock uncertainty

20%

CFGEE

Clock uncertainty

20%

CFGIE

Clock uncertainty

20%

INITRAMA

Clock uncertainty

20%

INITRAMB

Clock uncertainty

20%

LOCZRAMA

Clock uncertainty

20%

TEINIT

Clock uncertainty

20%

CFGNMFI

Clock uncertainty

20%

CFGATCMSZ[3:0]

Clock uncertainty

20%

CFGBTCMSZ[3:0]

Clock uncertainty

20%

PARECCENRAM[2:0]

Clock uncertainty

20%

ERRENRAM[2:0]

Summary of Contents for Cortex-R4

Page 2: ...e of the product ARM shall not be liable for any loss or damage arising from the use of any information in this document or any error or omission in such information or any incorrect use of the product Where the term ARM is used it means ARM or any of its subsidiaries as appropriate Some material in this document is based on ANSI IEEE Std 754 1985 IEEE Standard for Binary Floating Point Arithmetic...

Page 3: ...1 3 Features 1 4 1 4 Interfaces 1 5 1 5 Configurable options 1 6 1 6 Test features 1 10 1 7 Product documentation architecture and design flow 1 11 1 8 Product revisions 1 13 Chapter 2 Functional Description 2 1 About the functions 2 2 2 2 Interfaces 2 9 2 3 Clocking and resets 2 11 2 4 Operation 2 15 Chapter 3 Programmers Model 3 1 About the programmers model 3 2 3 2 Modes of operation and execut...

Page 4: ... 2 7 2 Memory types 7 7 7 3 Region attributes 7 8 7 4 MPU interaction with memory system 7 9 7 5 MPU faults 7 10 7 6 MPU software accessible registers 7 11 Chapter 8 Level One Memory System 8 1 About the L1 memory system 8 2 8 2 About the error detection and correction schemes 8 4 8 3 Fault handling 8 7 8 4 About the TCMs 8 13 8 5 About the caches 8 18 8 6 Internal exclusive monitor 8 34 8 7 Memor...

Page 5: ...ding VIC interface signals A 7 A 5 L2 interface signals A 8 A 6 TCM interface signals A 13 A 7 Redundant processor signals A 16 A 8 Debug interface signals A 17 A 9 ETM interface signals A 19 A 10 Test signals A 20 A 11 MBIST signals A 21 A 12 Validation signals A 22 A 13 FPU signals A 23 Appendix B AC Characteristics B 1 Processor timing B 2 B 2 Processor timing parameters B 3 Appendix C Cycle Ti...

Page 6: ...r transfer instructions C 29 C 20 Floating point load store instructions C 30 C 21 Floating point single precision data processing instructions C 32 C 22 Floating point double precision data processing instructions C 33 C 23 Dual issue C 34 Appendix D ECC Schemes D 1 ECC scheme selection guidelines D 2 Appendix E Revisions ...

Page 7: ... ARM Limited All rights reserved vii ID073015 Non Confidential Preface This preface introduces the Cortex R4 and Cortex R4F Technical Reference Manual It contains the following sections About this book on page viii Feedback on page xii ...

Page 8: ...ng or programming a System on Chip SoC that uses the processor Using this book This book is organized into the following chapters Chapter 1 Introduction Read this for an introduction to the processor and descriptions of the major functional blocks Chapter 2 Functional Description Read this for a description of the functionality of the processor Chapter 3 Programmers Model Read this for a descripti...

Page 9: ...Appendix A Signal Descriptions Read this for a description of the inputs and outputs of the processor Appendix B AC Characteristics Read this for a description of the timing parameters applicable to the processor Appendix C Cycle Timings and Interlock Behavior Read this for a description of the instruction cycle timing and instruction interlocks Appendix D ECC Schemes Read this for a description o...

Page 10: ...ume any timing information that is not explicit in the diagrams Shaded bus and signal areas are undefined so the bus or signal can assume any value within the shaded area at that time The actual level is unimportant and does not affect normal operation Key to timing diagram conventions Timing diagrams sometimes show single bit signals as HIGH and LOW at the same time and they look similar to the b...

Page 11: ...ion ARM IHI 0024 ARM Architecture Reference Manual ARMv7 A and ARMv7 R edition ARM DDI 0406 ARM PrimeCell Vectored Interrupt Controller PL192 Technical Reference Manual ARM DDI 0273 Cortex R4 and Cortex R4F Integration Manual ARM DII 0130 Cortex R4 and Cortex R4F Configuration and Sign off Guide ARM DII 0185 CoreSight Architecture Specification ARM IHI 0029 CoreSight DAP Lite Technical Reference M...

Page 12: ...r supplier and give The product name The product revision or version An explanation with as much information as you can provide Include symptoms and diagnostic procedures if appropriate Feedback on content If you have comments on content then send an e mail to errata arm com Give the title the number ARM DDI 0363G the page numbers to which your comments apply a concise explanation of your comments...

Page 13: ...r introduces the processor and its features It contains the following sections About the processor on page 1 2 Compliance on page 1 3 Features on page 1 4 Interfaces on page 1 5 Configurable options on page 1 6 Test features on page 1 10 Product documentation architecture and design flow on page 1 11 Product revisions on page 1 13 ...

Page 14: ...register file The processor has Tightly Coupled Memory TCM ports for low latency and deterministic accesses to local RAM in addition to caches for higher performance to general memory Error Checking and Correction ECC is used on the Cortex R4 processor ports and in Level 1 L1 memories to provide improved reliability and address safety critical applications Many of the features including the caches...

Page 15: ...tecture extensions Advanced Single Instruction Multiple Data SIMD architecture extension for integer and floating point vector operations Vector Floating Point version 3 VFPv3 architecture extension for floating point computation that is fully compliant with the IEEE 754 standard See the ARM Architecture Reference Manual 1 2 2 Trace macrocell The Cortex R4 processor implements the ETM v3 3 archite...

Page 16: ...cessor that includes the FPU A Harvard L1 memory system with optional Tightly Coupled Memory TCM interfaces with support for error correction or parity checking memories optional caches with support for optional error correction schemes optional ARMv7 R architecture Memory Protection Unit MPU optional parity and Error Checking and Correction ECC on all RAM blocks The ability to implement and use r...

Page 17: ... particularly from reset interrupt outputs providing information about the behavior of the processor to the wider system 32 bit APB slave interface and various debug handshake signals for connection to CoreSight components providing debug features ETM interface for connection to a CoreSight ETM R4 providing instruction and data trace Memory Built In Self Test MBIST interface and scan signals enabl...

Page 18: ...uration or pin configuration Redundant core Single core no redundancy Build Dual core redundant In phase clocks Out of phase clocks Build Instruction cache No Icache Build Icache included No error checking Parity error checking 64 bit ECC error checking Build 4KB 4x1KB ways 8KB 4x2KB ways 16KB 4x4KB ways 32KB 4x8KB ways 64KB 4x16KB ways Pin Data cache No Dcache Build Dcache included No error check...

Page 19: ...2x4MB Pin Interleaved on 64 bit granularity in memory Adjacent in memory Pin Instruction endianness Little endian Build Pin configured Little endian Big endian Pin Floating point VFP No FPU Build FPU includedb MPU No MPU Build MPU included 8 MPU regions 12 MPU regions Build TCM bus parity No TCM address and control bus parity Build TCM address and control bus parity generated AXI bus parity No AXI...

Page 20: ...TCM ports none one two is set by both build and pin configuration b Only available with the Cortex R4F processor c Only if the relevant TCM port s are included d Only if at least one TCM port is included and uses ECC error checking e Only relevant if at least one TCM port is included and uses parity error checking one of the caches includes parity checking or AXI or TCM bus parity is included Tabl...

Page 21: ...mparison logic to compare the outputs of the redundant logic and the functional logic These comparators can detect a single fault that occurs in either set of logic because of radiation or circuit failure When used in conjunction with RAM error detection schemes you can protect the system from faults The input signals DCCMINP 7 0 and DCCMINP2 7 0 and the output signals DCCMOUT 7 0 and DCCMOUT2 7 0...

Page 22: ...d TCM RAMs can be done through the dedicated pipelined MBIST interface This interface shares some of the multiplexing present in the processor design In addition you can use the AXI slave interface to read and write the cache RAMs and TCM You can use this feature to test the cache RAMs in a running system This might be required in a safety critical system The TCM can be read and written directly b...

Page 23: ...ration if any was performed before implementing the Cortex R4 processor the integrator to determine the pin configuration of the device that you are using Configuration and Sign off Guide The Configuration and Sign off Guide CSG describes the available build configuration options and related issues in selecting them how to configure the Register Transfer Level RTL with the build configuration opti...

Page 24: ...ons that affect how the RTL source files are pre processed These options usually include or exclude logic that affects one or more of the area maximum frequency and features of the resulting macrocell For example define the DUAL_CORE parameter to synthesize a second redundant copy of the processor and compare logic Configuration inputs The integrator configures some features of the Cortex R4 proce...

Page 25: ...oduct revisions r1p3 r1p4 Functional changes are The Revision field of the MIDR register changes to 0x4 See c0 Main ID Register on page 4 14 The Revision field of the FPSID register changes to 0x8 See Floating Point System ID Register on page 11 5 The Revision field of the Peripheral ID Register 2 changes to 0x8 See Peripheral ID Register 2 functions on page 12 40 Various engineering errata fixes ...

Page 26: ... 2 1 ID073015 Non Confidential Chapter 2 Functional Description This chapter describes the functionality of the processor It contains the following sections About the functions on page 2 2 Interfaces on page 2 9 Clocking and resets on page 2 11 Operation on page 2 15 ...

Page 27: ...tructions from the memory system predicts branches and passes instructions to the Data Processing Unit DPU The DPU executes all instructions and uses the Load Store Unit LSU for data memory transfers The PFU and LSU interface to the L1 memory system that contains L1 instruction and data caches and an interface to a L2 system The L1 memory can also contain optional TCM interfaces Processor Level tw...

Page 28: ...L2 memory interfaces 2 1 3 Prefetch unit The PFU obtains instructions from the instruction cache the TCMs or from external memory and predicts the outcome of branches in the instruction stream See Chapter 5 Prefetch Unit for more information Branch prediction The branch predictor is a global type that uses history registers and a 256 entry pattern history table Return stack The PFU includes a 4 en...

Page 29: ... 32 bytes MPU regions can overlap and the highest numbered region has the highest priority The MPU checks for protection and memory attributes and some of these can be passed to an external L2 memory system For more information see Chapter 7 Memory Protection Unit TCM interfaces There are two Tightly Coupled Memory TCM interfaces that permit connection to configurable blocks of TCM ATCM and BTCM T...

Page 30: ...AMs and TCMs through the AXI system bus You can use this for DMA into and out of the TCM RAMs and for software test of the cache RAMs The slave interface can run at the same frequency as the processor or at a lower synchronous frequency If asynchronous clocking is required an external asynchronous AXI slice is required Bits in the Auxiliary Control Register and Slave Port Control Register can cont...

Page 31: ...de On a debug event such as a breakpoint or watchpoint the debug logic stops the processor and forces it into debug state This enables you to examine the internal state of the processor and the external state of the system independently from other system activity When the debugging process completes the processor and system state are restored and normal program execution resumes Monitor debug mode...

Page 32: ...educe interrupt handler entry and exit time SRS Save return state to a specified stack frame RFE Return from exception using data from the stack CPS Change processor state such as interrupt mask setting and clearing and mode changes 2 1 9 Power management The processor includes several microarchitectural features to reduce energy consumption Accurate branch and return prediction reducing the numbe...

Page 33: ... externally After power up the assertion of reset returns the processor to the run state Standby mode This mode disables most of the clocks of the device while keeping the device powered up This reduces the power drawn to the static leakage current and the minimal clock power overhead required to enable the device to wake up from the Standby mode For more information on the power management featur...

Page 34: ...interfaces About the TCMs on page 8 13 describes the TCM interfaces TCM interface signals on page A 13 describes the associated signals 2 2 4 Interrupt and VIC interface Interrupts on page 3 16 describes the interrupts Interrupt signals including VIC interface signals on page A 7 describes the associated signals 2 2 5 Configuration interface Configuration signals on page A 4 describes the configur...

Page 35: ... and data trace for the processor The CoreSight ETM R4 Technical Reference Manual describes how the ETM R4 connects to the processor The ETM interface includes these signals an instruction interface a data interface an event interface other connections to the ETM ETM interface signals on page A 19 describes the associated signals Event bus interface on page 6 19 describes the event bus 2 2 9 Test ...

Page 36: ...ng instructions after reset All of these are active LOW signals that reset logic in the processor You must take care when designing the logic to drive these reset signals The processor synchronizes the resets to the relevant clock domains internally 2 3 2 Reset modes The reset signals in the processor enable you to reset different parts of the design independently Table 2 1 shows the reset signals...

Page 37: ... necessary to assert PRESETDBGn on power up Processor reset A processor or warm reset initializes the majority of the processor excluding the CoreSight logic Processor reset is typically used for resetting a system that is operating for some time for example watchdog reset Because the nRESET signal is synchronized within the processor you do not have to synchronize this signal ARM recommends that ...

Page 38: ...edge for which there is a simultaneous rising edge on the AXI system clock Figure 2 3 shows an example in which the processor is clocked at 400MHz CLKIN while the AXI system connected to the AXI master interface is clocked at 200MHz ACLKM The ACLKENM clock indicates the relationship between the two clocks Figure 2 3 AXI interface clocking If the AMBA system connected to an interface is clocked at ...

Page 39: ...FunctionalDescription ARM DDI 0363G Copyright 2006 2011 ARM Limited All rights reserved 2 14 ID073015 Non Confidential Figure 2 4 Standby wake up STANDBYWFI CPU_CLK CLKIN ATCEN0 ATCM_CLK ...

Page 40: ...on The reset values for the CP15 registers are described along with the registers in Chapter 4 System Control In addition before you run the application you might want to program particular values into various registers for example stack pointers enable various processor features for example error correction program particular values into memory for example the TCMs The following sections describe...

Page 41: ...an write data to the TCMs using either store instructions or the AXI slave interface Depending on the method you choose you might require particular hardware on the SoC that you are using boot code a debugger connected to the processor Methods to preload TCMs include Memory copy with running boot code The boot code includes a memory copy routine that reads data from a ROM and writes it into the ap...

Page 42: ... 4 bytes All bytes in the block must be written that is have their byte lane strobe asserted If the error scheme is 64 bit ECC the write transaction must start at a 64 bit aligned addresses and write a continuous block of memory containing a multiple of 8 bytes All bytes in the block must be written that is have their byte lane strobe asserted If initialization is done by running code on the proce...

Page 43: ...ocessor to boot from TCM but to do this the TCM must first be preloaded with the boot code The nCPUHALT pin can be asserted while the processor is in reset to stop the processor from fetching and executing instructions after coming out of reset While the processor is halted in this way the TCMs can be preloaded with the appropriate data When the nCPUHALT pin is deasserted the processor starts fetc...

Page 44: ...oprocessor It contains the following sections About the programmers model on page 3 2 Modes of operation and execution on page 3 3 Memory model on page 3 4 Data structures on page 3 5 Registers on page 3 6 Program status registers on page 3 9 Exceptions on page 3 14 Acceleration of execution environments on page 3 25 Unaligned and mixed endian data access support on page 3 26 Big endian instructio...

Page 45: ... 32 bit instructions For more information on the ARM and Thumb instruction sets see the ARM Architecture Reference Manual This chapter describes some of the main features of the architecture but for a complete description see the ARM Architecture Reference Manual This chapter also makes reference to older versions of the ARM architecture that the processor does not implement These references are i...

Page 46: ...r invokes the BX instruction Automatically on an exception You can write an exception handler routine in ARM or Thumb code For more information see Exceptions on page 3 14 Interworking ARM and Thumb state The processor enables you to mix ARM and Thumb code For more information about interworking ARM and Thumb see the RealView Compilation Tools Developer Guide 3 2 2 Operating modes In each state th...

Page 47: ...ual 3 3 1 Byte invariant big endian format In byte invariant big endian BE 8 format the processor stores the most significant byte of a word at the lowest numbered byte and the least significant byte at the highest numbered byte Figure 3 1 shows byte invariant big endian BE 8 format Figure 3 1 Byte invariant big endian BE 8 format 3 3 2 Little endian format In little endian format the lowest numbe...

Page 48: ...lue represents an integer in the range 2N 1 to 2N 1 1 using two s complement format For best performance you must align these data types in memory as follows doubleword quantities aligned to 8 byte boundaries doubleword aligned word quantities aligned to 4 byte boundaries word aligned halfword quantities aligned to 2 byte boundaries halfword aligned byte quantities can be placed on any byte bounda...

Page 49: ...ses register R13 as a Stack Pointer SP The SRS and RFE instructions use Register R13 Link Register Register R14 is used as the subroutine Link Register LR Register R14 receives the return address when a Branch with Link BL or BLX instruction is executed You can use R14 as a general purpose register at all other times The corresponding banked registers R14_svc R14_irq R14_fiq R14_abt and R14_und si...

Page 50: ...FIQ mode has seven banked registers mapped to R8 R14 R8_fiq R14_fiq As a result many FIQ handlers do not have to save any registers The Supervisor Abort IRQ and Undefined modes each have alternative mode specific registers mapped to R13 and R14 permitting a private stack pointer and link register for each mode Figure 3 3 on page 3 8 shows the register set and those registers that are banked Table ...

Page 51: ...n enables you to add high register values to low register values For more information see the ARM Architecture Reference Manual General registers and program counter System and User Program status registers banked register Supervisor Abort IRQ Undefined R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 FIQ R0 R1 R2 R3 R4 R5 R6 R7 R8_fiq R9_fiq R10_fiq R11_fiq R12_fiq R13_fiq R14_fiq R15 PC R0 ...

Page 52: ...it on page 3 12 The I and F bits on page 3 12 The T bit on page 3 12 The M bits on page 3 13 Modification of PSR bits by MSR instructions on page 3 13 3 6 1 The N Z C and V bits The N Z C and V bits are the condition code flags You can optionally set them with arithmetic and logical operations and also with MSR instructions and MRC instructions to R15 The processor tests these flags in accordance ...

Page 53: ...e status of the Q flag To determine the status of the Q flag you must read the PSR into a register and extract the Q flag from this For information of how the Q flag is set and cleared see individual instruction definitions in the ARM Architecture Reference Manual 3 6 3 The IT bits IT 7 5 encodes the base condition code for the current IT block if any It contains b000 when no IT block is active IT...

Page 54: ...r individual halfwords or bytes of the result as Table 3 2 shows Table 3 2 GE 3 0 settings GE 3 GE 2 GE 1 GE 0 Instruction A op B greater than or equal to C A op B greater than or equal to C A op B greater than or equal to C A op B greater than or equal to C Signed SADD16 31 16 31 16 0 31 16 31 16 0 15 0 15 0 0 15 0 15 0 0 SSUB16 31 16 31 16 0 31 16 31 16 0 15 0 15 0 0 15 0 15 0 0 SADDSUBX 31 16 1...

Page 55: ... For more information on how to use the A bit see Asynchronous abort masking on page 3 21 3 6 9 The I and F bits The I and F bits are the interrupt disable bits when the I bit is set IRQ interrupts are disabled when the F bit is set FIQ interrupts are disabled Software can use MSR CPS MOVS pc SUBS pc LDM pc or RFE instructions to change the values of the I and F bits They are also set automaticall...

Page 56: ...age 3 9 that are in this category are N Z C V Q GE 3 0 and E Bits that an MSR instruction must never modify and so must only be written as a side effect of another instruction If an MSR instruction tries to modify these bits the results are architecturally Unpredictable In the processor these bits are not affected The bits in Figure 3 4 on page 3 9 that are in this category are the execution state...

Page 57: ...on entry and exit summary Table 3 4 summarizes the PC value preserved in the relevant R14 on exception entry and the instruction that ARM recommends for exiting the exception handler Table 3 4 Exception entry and exit Exception or entry Recommended return instruction Previous state Notes ARMR14_x Thumb R14_x SVCa MOVS PC R14_svc IA 4 IA 2 Where the IA is the address of the SVC or Undefined instruc...

Page 58: ...next instruction from the relevant exception vector The processor can also set the interrupt disable flags to prevent otherwise unmanageable nesting of exceptions Leaving an exception When an exception has completed the exception handler must move the LR minus an offset to the PC The offset varies according to the type of exception as Table 3 4 on page 3 14 shows Typically the return instruction i...

Page 59: ...latency that is the time taken between the assertion of the interrupt input and the execution of the interrupt handler By default the processor uses the Low Interrupt Latency LIL behaviors introduced in version 6 and later of the ARM architecture The processor also has a port for connection of a Vectored Interrupt Controller VIC and supports Non Maskable Fast Interrupts NMFI The following subsecti...

Page 60: ...always taken as quickly as possible except during handling of a fast interrupt This makes the fast interrupt suitable for signaling critical events NMFI behavior is controlled by a configuration input signal CFGNMFI that is asserted HIGH to enable NMFI operation There is no software control of NMFI Software can detect whether NMFI operation is enabled by reading the NMFI bit of the SCTLR NMFI 0 So...

Page 61: ...ese features software is still required to determine from the interrupt controller which interrupt source is requesting service determine where the service routine for that interrupt source is loaded mask or clear that interrupt source before re enabling processor interrupts to permit another interrupt to be taken A VIC does all these in hardware to reduce the interrupt latency It supplies the sta...

Page 62: ...rol Register on page 4 37 LR_fiq RA 4 CPSR 4 0 FIQ mode CPSR 5 TE CPSR 7 1 CPSR 6 1 SPSR_fiq CPSR V 1 FALSE TRUE FALSE nFIQ F nIRQ I nFIQ F VE 1 FALSE V 1 TRUE PC 31 0 Handler address provided by VIC Acknowledge address to VIC TRUE FALSE Is VIC ready to provide handler address FALSE TRUE TRUE Start handshake with VIC LR_irq RA 4 SPSR_irq CPSR CPSR 4 0 IRQ mode FALSE CPSR 7 1 CPSR 5 TE VE 1 PC 31 0...

Page 63: ...ample because a branch occurs while it is in the pipeline the abort does not take place All prefetch aborts are synchronous Data aborts An error occurring on a data memory access can generate a data abort If the instruction generating the memory access is not executed for example because it fails its condition codes or is interrupted the data abort does not take place A Data Abort DABT can be eith...

Page 64: ... is set any asynchronous abort that occurs is held pending by the processor until the A bit is cleared when the exception is actually taken The A bit is automatically set when abort IRQ or FIQ exceptions are taken and on reset You must only clear the A bit in an abort handler after the state information has either been stacked to memory or is no longer required Only one pending asynchronous abort ...

Page 65: ...f repeating accesses are inconsequential the error must either occur on the first word accessed or not at all The instructions that this rule applies to are All forms of ARM instructions LDM and LDRD all forms of STM STRD including VFP variants and unaligned LDR STR LDRH and STRH Thumb instructions LDMIA LDRD SDRD PUSH POP and STMIA including VFP variants and unaligned LDR STR LDRH and STRH Abort ...

Page 66: ...12 0 Obtain the instruction that caused the Undefined Instruction exception and return correctly after it Exception handlers must also be aware of the potential for both 16 bit and 32 bit instructions in Thumb state After testing the SPSR and determining the instruction was executed in Thumb state the Undefined handler must use the following pseudo code or equivalent to obtain this information add...

Page 67: ...ble 3 6 shows the exception vector addresses and entry conditions for the different exception types Table 3 5 Configuration of exception vector address locations Value of V bit Exception vector base location 0 0x00000000 1 HIVECS 0xFFFF0000 Table 3 6 Exception vectors Exception Offset from vector base Mode on entry A bit on entry F bit on entry I bit on entry Reset 0x00 Supervisor Set Set Set Unde...

Page 68: ...instruction summary and the response to the instructions Note Because no hardware acceleration is present in the processor when the BXJ instruction is used the BX instruction is invoked Table 3 7 Jazelle register instruction summary Register Instruction Response Jazelle ID MRC p14 7 Rd c0 c0 0 MCR p14 7 Rd c0 c0 0 Read as zero Ignore writes Jazelle main configuration MRC p14 7 Rd c2 c0 0 MCR p14 7...

Page 69: ...accesses Unaligned memory accesses was introduced with ARMv6 Bit 22 of c1 Control Register is always 1 The processor supports byte invariant big endianness BE 8 and little endianness LE The processor does not support word invariant big endianness BE 32 Bit 7 of c1 Control Register is always 0 For more information on unaligned and mixed endian data access support see the ARM Architecture Reference ...

Page 70: ... SCTLR For more information see c1 System Control Register on page 4 37 Note The facility to use big endian or little endian instruction format is an implementation option and you can therefore remove it in specific implementations If this facility is not present the CFGIE pin is still reflected in the SCTLR but the instruction format is always little endian The Build Options Register indicates wh...

Page 71: ...on Confidential Chapter 4 System Control This chapter describes the purpose of the system control coprocessor its structure operation and how to use it It contains the following sections About system control on page 4 2 Register summary on page 4 7 Register descriptions on page 4 9 ...

Page 72: ...gram flow prediction coprocessor access rights for CP0 CP13 including the VFP CP10 11 The system identification control and configuration registers also provide the processor ID and information on configured options The system identification control and configuration registers consist of 18 read only registers and seven read write registers Figure 4 1 shows the arrangement of registers in this fun...

Page 73: ...caches control cache maintenance operations that include clean and invalidate caches drain and flush buffers and address translation override cache behavior during debug or interruptible cache operations The cache control and configuration registers consist of three read only registers one read write register and a number of write only registers Figure 4 3 on page 4 4 shows the arrangement of the ...

Page 74: ...The performance monitor registers control the monitoring operation count events The system performance monitor consists of 12 read write registers Figure 4 5 on page 4 5 shows the arrangement of registers in this functional group Opcode_2 CRm Opcode_1 1 c0 0 c0 Cache Type Register CRn c7 Cache Operations Registers See description of cache operations for operations with User mode access Invalidate ...

Page 75: ...The system validation registers consist of nine read write registers and one write only register Figure 4 6 shows the arrangement of registers Figure 4 6 System validation registers Opcode_2 CRm CRn Opcode_1 c9 0 0 c12 Overflow Flag Status Register Count Enable Set Register Count Enable Clear Register Performance Monitor Control Register Event Select Register Performance Counter Selection Register...

Page 76: ...emControl ARM DDI 0363G Copyright 2006 2011 ARM Limited All rights reserved 4 6 ID073015 Non Confidential You can only change the cache size to a size supported by the cache RAMs implemented in your design ...

Page 77: ...ter order and gives the reset value for each register Table 4 1 System control coprocessor register functions Function Register operation Reference to description System identification control and configuration Control c1 System Control Register on page 4 37 Auxiliary control c1 Auxiliary Control Register on page 4 40 Coprocessor Access Control c1 Coprocessor Access Register on page 4 46 Main IDa ...

Page 78: ...lt Location register Correctable Fault Location Register on page 4 75 Cache control and configuration Cache Type c0 Cache Type Register on page 4 15 Current Cache Size Identification c0 Current Cache Size Identification Register on page 4 34 Current Cache Level c0 Current Cache Level ID Register on page 4 35 Cache Size Selection c0 Cache Size Selection Register on page 4 36 c7 Cache Operations Cac...

Page 79: ...ID Read only 0x41xFC14xa page 4 14 1 Cache Type Read only 0x8003C003 page 4 15 2 TCM Type Read only 0x00010001 page 4 16 4 MPU Type Read only b page 4 17 5 Multiprocessor Affinity Read only d page 4 18 c1 0 Processor Feature 0 Read only 0x00000131 page 4 18 1 Processor Feature 1 Read only 0x00000001 page 4 19 2 Debug Feature 0 Read only 0x00010400 page 4 20 3 Auxiliary Feature 0 Read only 0x000000...

Page 80: ...on Fault Status Read write Unpredictable page 4 49 2 7 Undefined c1 0 Auxiliary Data Fault Status Read write Unpredictable page 4 49 c5 0 c1 1 Auxiliary Instruction Fault Status Read write Unpredictable page 4 49 2 7 Undefined c2 c15 0 7 c6 0 c0 0 Data Fault Address Read write Unpredictable page 4 51 1 Undefined 2 Instruction Fault Address Read write Unpredictable page 4 51 3 7 Undefined c1 0 MPU ...

Page 81: ...validate entire branch predictor array Write only page 4 59 7 Invalidate address from branch predictor array Write only page 4 59 c6 0 Undefined 1 Invalidate data cache line by physical address Write only page 4 59 2 Invalidate data cache line by Set Way Write only page 4 59 3 7 Undefined c7 9 0 7 c10 0 1 Clean data cache line by physical address Write only page 4 59 2 Clean data cache line by Set...

Page 82: ... page 4 61 2 7 Undefined c2 0 TCM selection Read write 0x00000000 page 4 63 1 7 Undefined c3 c11 0 7 c12 0 Performance Monitor Control Read write 0x41141800 page 6 7 1 Count Enable Set Read write Unpredictable page 6 8 2 Count Enable Clear Read write Unpredictable page 6 9 3 Overflow Flag Status Read write Unpredictable page 6 11 4 Software Increment Write only page 6 12 c9 0 c12 5 Performance Cou...

Page 83: ...0 page 4 65 4 Privileged Only Thread and Process ID Read write 0x00000000 page 4 65 5 7 Undefined c13 0 c1 c15 0 7 Undefined c14 0 c0 c15 0 7 c15 0 c0 0 Secondary Auxiliary Control Read write d page 4 43 1 7 Undefined c1 0 nVAL IRQ Enable Set Read write Unpredictable page 4 66 1 nVAL FIQ Enable Set Read write Unpredictable page 4 67 2 nVAL Reset Enable Set Read write Unpredictable page 4 68 3 nVAL...

Page 84: ...e 4 78 2 7 Undefined c3 0 Correctable Fault Location Read write Unpredictable page 4 75 1 7 Undefined c4 0 7 c5 0 Invalidate all data cache Write only page 4 59 1 7 Undefined c6 c13 0 7 c15 0 c14 0 Cache Size Override Write only page 4 74 1 7 Undefined c15 0 7 a The value of bits 23 20 3 0 of the MIDR depend on product revision See the register description for more information b Reset value depend...

Page 85: ...The CTR is a read only register accessible in Privileged mode only Configurations Available in all processor configurations Attributes See Table 4 4 on page 4 16 Figure 4 8 shows the CTR bit assignments Figure 4 8 CTR Register bit assignments Table 4 3 MIDR Register bit assignments Bits Name Function 31 24 Implementer Indicates implementer 0x41 ARM Limited 23 20 Variant Identifies the major revisi...

Page 86: ...CMTR Register bit assignments Table 4 4 CTR Register bit assignments Bits Name Function 31 28 Always b1000 27 24 CWG Cache Write back Granule 0x0 no information provided See maximum cache line size in c0 Current Cache Size Identification Register on page 4 34 23 20 ERG Exclusives Reservation Granule 0x0 no information provided 19 16 DMinLine Indicates log2 of the number of words in the smallest ca...

Page 87: ...from both instruction and data sides 4 3 5 c0 MPU Type Register The MPUIR characteristics are Purpose Holds the value for the number of instruction and data memory regions implemented in the processor Usage constraints The MPUIR is a read only register accessible in Privileged mode only Configurations Available in all processor configurations Attributes See Table 4 6 on page 4 18 Figure 4 10 shows...

Page 88: ...on 4 3 7 The Processor Feature Registers The processor has two Processor Feature Registers PFR0 and PFR1 This section describes c0 Processor Feature Register 0 c0 Processor Feature Register 1 on page 4 19 c0 Processor Feature Register 0 The PFR0 characteristics are Purpose Provides information about the execution state support and programmers model for the processor Usage constraints PFR0 is a rea...

Page 89: ...2 shows the PFR1 bit assignments Figure 4 12 PFR1 Register bit assignments Reserved State3 31 16 15 8 7 3 0 State2 State1 State0 4 11 12 Table 4 7 PFR0 Register bit assignments Bits Name Function 31 16 SBZ 15 12 State3 Indicates support for Thumb Execution Environment ThumbEE 0x0 no support 11 8 State2 Indicates support for acceleration of execution environments in hardware or software 0x1 the pro...

Page 90: ... 4 9 on page 4 21 Figure 4 13 shows the ID_DFR0 bit assignments Figure 4 13 ID_DFR0 Register bit assignments Table 4 8 PFR1 bit assignments Bits Name Function 31 12 SBZ 11 8 Microcontroller programmers model Indicates support for Microcontroller programmers model 0x0 no support 7 4 Security extension Indicates support for Security Extensions architecture 0x0 no support 3 0 ARMv4 Programmers model ...

Page 91: ...egister 0 on page 4 22 c0 Memory Model Feature Register 1 on page 4 23 c0 Memory Model Feature Register 2 on page 4 24 c0 Memory Model Feature Register 3 on page 4 25 Table 4 9 ID_DFR0 Register bit assignments Bits Name Function 31 24 SBZ 23 20 Microcontroller Debug model memory mapped Indicates support for the microcontroller debug model memory mapped 0x0 no support 19 16 Trace debug model memory...

Page 92: ...ability Table 4 10 ID_MMFR0 Register bit assignments Bits Name Function 31 28 Innermost shareability Indicates the innermost shareability domain implemented RAZ UNK because only one shareability domain is implemented see bits 15 12 27 24 FCSE Indicates support for Fast Context Switch Extension FCSE 0x0 no support 23 20 Auxiliary Registers Indicates support for the auxiliary registers 0x2 the proce...

Page 93: ...ance operations Set and Way unified L1 cache line maintenance operations Set and Way Harvard L1 cache line maintenance operations MVA unified L1 cache line maintenance operations MVA Harvard Branch predictor Table 4 11 ID_MMFR1 Register bit assignments Bits Name Function 31 28 Branch predictor Indicates Branch Predictor management requirements 0x0 no MMU present 27 24 L1 test clean operations Indi...

Page 94: ...signments 11 8 L1 cache line maintenance operations Set and Way Harvard Indicates support for L1 cache line maintenance operations by Set and Way Harvard architecture 0x0 no support 7 4 L1 cache line maintenance operations MVA unified Indicates support for L1 cache line maintenance operations by address unified architecture 0x0 no support 3 0 L1 cache line maintenance operations MVA Harvard Indica...

Page 95: ...s Flag 0x0 no support 27 24 WFI Indicates support for Wait For Interrupt stalling 0x1 the processor supports Wait For Interrupt 23 20 Memory barrier Indicates support for memory barrier operations 0x2 the processor supports DSB formerly DWB ISB formerly Prefetch Flush DMB 19 16 TLB maintenance operations unified Indicates support for TLB maintenance operations unified architecture 0x0 no support 1...

Page 96: ...SA implementation 27 24 SBZ 23 20 Coherent walk RAZ because this is a PMSA implementation 19 16 SBZ 15 12 Maintenance broadcast Indicates whether cache maintenance operations are broadcast 0x0 cache maintenance operations only affect local structures 11 8 Branch predictor maintenance operations Indicates support for branch predictor maintenance operations in systems with hierar chical cache mainte...

Page 97: ..._ISAR0 Register bit assignments Table 4 14 shows the ID_ISAR0 bit assignments Reserved 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 Divide instructions Debug instructions Coprocessor instructions Compare and branch instructions Bitfield instructions Bit count instructions Atomic instructions Table 4 14 ID_ISAR0 Register bit assignments Bits Name Function 31 28 SBZ 27 24 Divide instructions Indicates...

Page 98: ...re 4 19 shows the ID_ISAR1 bit assignments Figure 4 19 ID_ISAR1 Register bit assignments 11 8 Bitfield instructions Indicates support for bitfield instructions 0x1 the processor supports bitfield instructions BFC BFI SBFX and UBFX 7 4 Bit counting instructions Indicates support for bit counting instructions 0x1 the processor supports CLZ 3 0 Atomic instructions Indicates support for atomic load an...

Page 99: ... T bit in PSRs BLX and PC loads have BX behavior data processing instructions in the ARM instruction set with the PC as the destination and the S bit clear have BX like behavior 23 20 Immediate instructions Indicates support for immediate instructions 0x1 the processor supports the MOVT instruction MOV instruction encodings with 16 bit immediates Thumb ADD and SUB instructions with 12 bit immediat...

Page 100: ...rsal instructions Indicates support for reversal instructions 0x2 the processor supports REV REV16 REVSH and RBIT 27 24 PSR instructions Indicates support for PSR instructions 0x1 the processor supports MRS and MSR and the exception return forms of data processing instructions 23 20 Unsigned multiply instructions Indicates support for advanced unsigned multiply instructions 0x2 the processor suppo...

Page 101: ... the ID_ISAR3 bit assignments Figure 4 21 ID_ISAR3 Register bit assignments 11 8 Interruptible instructions Indicates support for multi access interruptible instructions 0x1 the processor supports restartable LDM and STM 7 4 Memory hint instructions Indicates support for memory hint instructions 0x3 the processor supports PLD and PLI 3 0 Load store instructions Indicates support for additional loa...

Page 102: ...ts 23 20 Thumb copy instructions Indicates support for Thumb copy instructions 0x1 the processor supports Thumb MOV 3 low register to low register 19 16 Table branch instructions Indicates support for table branch instructions 0x1 the processor supports table branch instructions TBB and TBH 15 12 Synchronization primitive instructions Indicates support for synchronization primitive instructions 0x...

Page 103: ... because SWP SWPB instruction support is indicated in ID_ISAR0 27 24 PSR_M_instrs Indicates support for M profile instructions for modifying the PSRs 0x0 no support 23 20 Exclusive instructions Indicates support for Exclusive instructions 0x0 Only supports synchronization primitive instructions as indicated by bits 15 12 in the ISAR3 register See c0 Instruction Set Attributes Register 3 on page 4 ...

Page 104: ...hes This processor contains L1 instruction and data caches only The CSSELR determines which CCSIDR to select see c0 Cache Size Selection Register on page 4 36 Usage constraints The CCSIDR is a read only register accessible in Privileged mode only Configurations Available in all processor configurations Attributes See Table 4 19 Figure 4 23 shows the CCSIDR bit assignments Figure 4 23 CCSIDR Regist...

Page 105: ...emented Architecturally there can be a different number of cache levels on the instruction and data side Captures the point of coherency Captures the point of unification Usage constraints The CLIDR is a read only register accessible in Privileged mode only Configurations Available in all processor configurations Attributes See Table 4 21 on page 4 36 27 13 NumSets Indicates the number of sets as ...

Page 106: ...7 15 14 12 11 10 8 6 5 3 2 0 LoU LoC Table 4 21 CLIDR Register bit assignments Bits Name Function 31 30 SBZ 29 27 LoU Level of Unification 0b001 L2 if either cache is implemented 0b000 L1 if neither instruction nor data cache is implemented 26 24 LoC Level of Coherency 0b001 L2 if either cache is implemented 0b000 L1 if neither instruction nor data cache is implemented 23 21 CL 8 0b000 no cache at...

Page 107: ...tion and fault behavior MPU and cache enables and cache replacement strategy interrupts and the behavior of interrupt latency the location for exception vectors program flow prediction Usage constraints The SCTLR is a read write register accessible in Privileged mode only attempts to read or write the SCTLR from User mode result in an Undefined Instruction exception Configurations Available in all...

Page 108: ...eption generation The primary input TEINIT defines the reset value 29 AFE Access Flag Enable On the processor this bit is SBZ 28 TRE TEX Remap Enable On the processor this bit is SBZ 27 NMFI NMFI non maskable fast interrupt enable 0 Software can disable FIQs 1 Software cannot disable FIQs This bit is read only The configuration input CFGNMFI defines its value 26 SBZ 25 EE Determines how the E bit ...

Page 109: ...d address range 0x00000000 0x0000001C 1 high exception vectors HIVECS selected address range 0xFFFF0000 0xFFFF001C The primary input VINITHI defines the reset value 12 I Enables L1 instruction cache 0 instruction caching disabled This is the reset value 1 instruction caching enabled If no instruction cache is implemented then this bit is SBZ 11 Z Branch prediction enable bit The processor supports...

Page 110: ...s 31 28 or 7 is followed by an ISB instruction to ensure that the changes have taken effect before any dependent instructions are executed Configurations Available in all processor configurations Attributes See Table 4 24 on page 4 41 Figure 4 27 shows the ACTLR bit assignments Figure 4 27 ACTLR Register bit assignments 31 25 24 23 22 21 19 18 17 16 15 14 13 12 11 7 6 3 2 1 0 CEC 26 27 28 30 29 DI...

Page 111: ...as B0TCMPCEN 26 B0TCMPCEN B0TCM parity or ECC check enable 0 Disabled 1 Enabled The primary input PARECCENRAM 1 b defines the reset value If the BTCM is configured with ECC you must always set this bit to the same value as B1TCMPCEN 25 ATCMPCEN ATCM parity or ECC check enable 0 Disabled 1 Enabled The primary input PARECCENRAM 0 b defines the reset value 24 AXISCEN AXI slave cache RAM access enable...

Page 112: ...This is the reset value 1 Disable write burst optimization 13 DLFO Disable linefill optimization in the AXI master 0 Normal operation This is the reset value 1 Limits the number of outstanding data linefills to two 12 ERPEGc Enable random parity error generation 0 Random parity error generation disabled This is the reset value 1 Enable random parity error generation in the cache RAMs Note This bit...

Page 113: ...hed 0 Normal operation This is the reset value 1 sMOV out of order disabled 6 DILS Disable low interrupt latency on all load store instructions 0 Enable LIL on all load store instructions This is the reset value 1 Disable LIL on all load store instructions 5 3 CEC Cache error control for cache parity and ECC errors See Table 8 2 on page 8 21 and Table 8 3 on page 8 22 for information about how the...

Page 114: ...22 21 19 18 17 16 15 14 13 12 11 7 3 2 1 0 10 20 9 4 8 DR2B DF6DI DF2DI DOODPFP DDI ATCMRMW ATCMECC IDC DZC IOC UFC OFC IXC DOOFMACS BTCMRMW B0TCMECC Reserved DCHE 23 Table 4 25 Secondary Auxiliary Control Register bit assignments Bits Name Function 31 23 SBZ 22 DCHE Disable hard error support in the caches a 0 Enabled The cache logic recovers from some hard errors You must not use this value on r...

Page 115: ...nderflow exception output mask c 0 Mask floating point underflow exception output The output FPUFC is forced to zero This is the reset value 1 Propagate floating point underflow exception flag FPSCR UFC to output FPUFC 10 IOC Floating point invalid operation exception output mask c 0 Mask floating point invalid operation exception output The output FPIOC is forced to zero This is the reset value 1...

Page 116: ... 4 47 Figure 4 29 on page 4 47 shows the CPACR bit assignments 2 ATCMECC Correction for internal ECC logic on ATCM port d 0 Enabled This is the reset value 1 Disabled 1 BTCMRMW Enables 64 bit stores for the BTCMs When enabled the processor uses read modify write to ensure that all reads and writes presented on the BTCM ports are 64 bits wide e 0 Disabled 1 Enabled The primary input RMWENRAM 1 defi...

Page 117: ...8 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cp13 cp12 cp11 cp10 cp9 cp8 cp7 cp6 cp5 cp4 cp3 cp2 cp1 cp0 Table 4 26 CPACR Register bit assignments Bits Name Function 31 28 SBZ 27 0 cp n a Defines access permissions for each coprocessor Access denied is the reset condition and is the behavior for non existent coprocessors b00 Access denied Attempts to access generates an Undefined Instruction exce...

Page 118: ...12 13 RW SD Table 4 28 DFSR Register bit assignments Bits Name Function 31 13 SBZ 12 SD Distinguishes between an AXI Decode or Slave error on an external abort This bit is only valid for external aborts For all other aborts types of abort this bit is set to zero 0 AXI Decode error DECERR caused the abort 1 AXI Slave error SLVERR or OKAY in response to exclusive read transaction caused the abort 11...

Page 119: ...s Registers The processor has two auxiliary fault status registers the Auxiliary Data Fault Status Register ADFSR S Reserved 31 3 0 Status Domain 4 9 10 11 12 13 Reserved SD 8 7 Reserved Table 4 29 IFSR Register bit assignments Bits Name Function 31 13 SBZ 12 SD Distinguishes between an AXI Decode or Slave error on an external abort This bit is only valid for external aborts For all other aborts t...

Page 120: ...le 4 30 shows the auxiliary fault status register bit assignments To access the auxiliary fault status registers read or write CP15 with Reserved Index Reserved 31 0 Reserved 4 27 24 23 22 14 13 5 CacheWay Side 28 21 20 Recoverable error Table 4 30 Auxiliary fault status register bit assignments Bits Name Function 31 28 SBZ 27 24 CacheWaya The value returned in this field indicates the cache way o...

Page 121: ... data written This is useful for a debugger to restore the value of the DFAR The processor also updates the DFAR on debug exception entry because of watchpoints See Effect of debug exceptions on CP15 registers and DBGWFAR on page 12 45 for more information c6 Instruction Fault Address Register The IFAR characteristics are Purpose Holds the address of the instruction that caused a prefetch abort Us...

Page 122: ...u must define at least one of the regions in the MPU An access to an undefined area of memory normally generates a background fault For the TCM space the processor uses the access permissions but ignores the region attributes from MPU CP15 c9 sets the location of the TCM base address For more information see c9 BTCM Region Register on page 4 61 and c9 ATCM Region Register on page 4 62 c6 MPU Regio...

Page 123: ... the address ranges that are used for a particular region Enables or disables the region and its sub regions specified by the Memory Region Number Register Usage constraints The MPU Region Size and Enable Registers are 32 bit read write registers accessible in Privileged mode only Configurations Use these registers if the processor is configured with an MPU Attributes See Table 4 32 on page 4 54 F...

Page 124: ... Control Registers bit assignments Table 4 32 Region Size MPU Region Size and Enable Registers bit assignments Bits Name Function 31 16 SBZ 15 8 Sub region disable Each bit position represents a sub region 0 7a Bit 8 corresponds to sub region 0 Bit 15 corresponds to sub region 7 The meaning of each bit is 0 address range is part of this region 1 address range is not part of this region SBZ 5 1 Reg...

Page 125: ... access permissions For more information on AP bit values see Table 4 36 on page 4 56 7 6 SBZ 5 3 TEX Type extension Defines the type extension attributea 2 S Share Determines if the memory region is Shared or Non shared 0 Non shared 1 Shared This bit only applies to Normal not Device or Strongly ordered memory 1 C C bita 0 B B bita a For more information on this region attribute see Table 4 34 Ta...

Page 126: ...ecified as Write back cacheable no write allocate memory accesses to this type of memory behave as Write Back Write Allocate behavior for a memory c Table 4 35 shows the encoding for these bits Table 4 34 TEX 2 0 C and B encodings continued TEX 2 0 C B Description Memory Type Shareable Table 4 35 Inner and Outer cache policy encoding Memory attribute encoding Cache policy 00 Non cacheable 01 Write...

Page 127: ...ed mode only Writing this register with a value greater than or equal to the number of regions from the MPUIR is Unpredictable Associated MPU Region Register accesses are also Unpredictable Configurations Use this register if the processor is configured with an MPU Attributes See Table 4 37 Figure 4 36 shows the RGNR bit assignments Figure 4 36 RGNR Register bit assignments Table 4 37 shows the RG...

Page 128: ...where all instruction and data walks are transparent to any processor in the system Point of Unification PoU A point where instruction and data become unified and self modifying code can function Figure 4 37 on page 4 59 shows the arrangement of the functions in this group that operate with the MCR and MRC instructions Note The following operations as Figure 4 37 on page 4 59 shows are implemented...

Page 129: ... describe the invalidate clean and prefetch operations are defined in the ARM Architecture Reference Manual You can perform invalidate and clean operations on single cache lines entire caches Set and Way format Figure 4 38 on page 4 60 shows the Set and Way bit assignments c7 SBZ SBZ MVA SBZ MVA Way MVA Way SBZ SBZ MVA Way Invalidate data cache line by set way Invalidate data cache line to Point o...

Page 130: ...ws the invalidate and clean operations bit assignments Way 0 Set Reserved Reserved 5 4 S 4 S 5 31 29 30 Table 4 38 Set and Way bit assignments Bits Name Function 31 30 Way Indicates the cache way to invalidate or clean 29 S 5 SBZ S 4 5 Set Indicates the cache set to invalidate or clean Because the cache sizes are configurable the width of the Set field is unique to the cache size See Table 4 39 4 ...

Page 131: ...ensure that all outstanding explicit memory transactions complete before any following explicit memory transactions begin This ensures that data in memory is up to date before any memory transaction that depends on it The Data Memory Barrier operation is write only accessible in User and Privileged mode To access the Data Memory Barrier operation write CP15 with MCR p15 0 Rd c7 c10 5 Data Memory B...

Page 132: ...igure 4 41 ATCM Region Register bit assignments Table 4 41 BTCM Region Register bit assignments Bits Name Function 31 12 Base address Base address Defines the base address of the BTCM The base address must be aligned to the size of the BTCM Any bits in the range log2 RAMSize 1 12 are ignored At reset if LOCZRAMA is set to 0 The initial base address is 0x0 1 The initial base address is implementati...

Page 133: ...nstraints The Slave Port Control Register is a read write register accessible in Privileged mode only Configurations Available in all processor configurations Attributes See Table 4 43 on page 4 64 Figure 4 42 on page 4 64 shows the Slave Port Control Register bit assignments Table 4 42 ATCM Region Register bit assignments Bits Name Function 31 12 Base address Base address Defines the base address...

Page 134: ...ng process The Embedded Trace Macrocell ETM and the debug logic use this register The ETM can broadcast its value to indicate the process that is running You must program each process with a unique number Enables process dependent breakpoints and instructions Usage constraints The CONTEXTIDR is a read write register accessible in Privileged mode only Configurations Available in all processor confi...

Page 135: ...en in Privileged modes The Privileged only register can be read and written in Privileged modes only To access the Thread and Process ID registers read or write CP15 with MRC p15 0 Rd c13 c0 2 Read User read write Thread and Proc ID Register MCR p15 0 Rd c13 c0 2 Write User read write Thread and Proc ID Register MRC p15 0 Rd c13 c0 3 Read User Read Only Thread and Proc ID Register MCR p15 0 Rd c13...

Page 136: ...Purpose Enables any of the PMXEVCNTR Registers PMXEVCNTR0 PMXEVCNTR2 and PMCCNTR to generate an interrupt request on overflow If enabled the interrupt request is signaled by nVALIRQ being asserted LOW Usage constraints The nVAL IRQ Enable Set Register is A read write register Always accessible in Privileged mode The PMUSERENR Register determines access in User mode see c9 User Enable Register on p...

Page 137: ... FIQ Enable Set Register The nVAL FIQ Enable Set Register characteristics are Purpose Enables any of the PMXEVCNTR Registers PMXEVCNTR0 PMXEVCNTR2 and PMCCNTR to generate an fast interrupt request on overflow If enabled the interrupt request is signaled by nVALFIQ being asserted LOW Usage constraints The nVAL FIQ Enable Set Register is A read write register Always accessible in Privileged mode The...

Page 138: ...Enable Set Register The nVAL Reset Enable Set Register is A read write register Always accessible in Privileged mode The PMUSERENR Register determines access in User mode see c9 User Enable Register on page 6 15 The nVAL Reset Enable Set Register characteristics are Purpose Enables any of the PMXEVCNTR Registers PMXEVCNTR0 PMXEVCNTR2 and PMCCNTR to generate a reset request on overflow If enabled t...

Page 139: ...be passed to a system reset controller c15 VAL Debug Request Enable Set Register The VAL Debug Request Enable Set Register characteristics are Purpose Enables any of the PMXEVCNTR Registers PMXEVCNTR0 PMXEVCNTR2 and PMCCNTR to generate a debug request on overflow If enabled the debug request is signaled by VALEDBGRQ being asserted HIGH Usage constraints The VAL Debug Request Enable Set Register is...

Page 140: ...request is indicated by VALEDBGRQ being asserted HIGH This signal can be passed to an external debugger c15 nVAL IRQ Enable Clear Register The nVAL IRQ Enable Clear Register characteristics are Purpose Disables overflow IRQ requests from any of the PMXEVCNTR Registers PMXEVCNTR0 PMXEVCNTR2 and PMCCNTR for which they have been enabled Usage constraints The nVAL IRQ Enable Clear Register is A read w...

Page 141: ...AL FIQ Enable Clear Register The nVAL FIQ Enable Clear Register characteristics are Purpose Disables overflow FIQ requests from any of the PMXEVCNTR Registers PMXEVCNTR0 PMXEVCNTR2 and PMCCNTR that are enabled Usage constraints The nVAL FIQ Enable Clear Register is A read write register Always accessible in Privileged mode The PMUSERENR Register determines access in User mode see c9 User Enable Re...

Page 142: ... Clear Register The nVAL Reset Enable Clear Register characteristics are Purpose Disables overflow reset requests from any of the PMXEVCNTR Registers PMXEVCNTR0 PMXEVCNTR2 and PMCCNTR that are enabled Usage constraints The nVAL Reset Enable Clear Register is A read write register Always accessible in Privileged mode The PMUSERENR Register determines access in User mode see c9 User Enable Register ...

Page 143: ...e Clear Register The VAL Debug Request Enable Clear Register characteristics are Purpose Disables overflow debug requests from any of the PMXEVCNTR Registers PMXEVCNTR0 PMXEVCNTR2 and PMCCNTR that are enabled Usage constraints The VAL Debug Request Enable Clear Register is A read write register Always accessible in Privileged mode The PMUSERENR Register determines access in User mode see c9 User E...

Page 144: ...ge 4 69 c15 Cache Size Override Register The Cache Size Override Register characteristics are Purpose Overwrites the caches size fields in the main register This enables you to choose a smaller instruction and data cache size than is implemented Usage constraints The Cache Size Override Register is a write only register only accessible in Privileged mode Configurations Available in all processor c...

Page 145: ...e CFLR characteristics are Purpose Indicates the location of the last correctable error that occurred during cache or TCM operations Usage constraints The CFLR is a read write register accessible in Privileged mode only not updated on speculative accesses for example an instruction fetch for an instruction that is not executed because of a previous branch a TCM external error or external retry req...

Page 146: ...rs You can read bits 25 24 to determine whether the error was from a cache or TCM access Figure 4 52 shows the CFLR bit assignments when it indicates a correctable cache error Figure 4 52 CFLR cache bit assignments Table 4 54 shows the CFLR bit assignments when it indicates a correctable cache error Figure 4 53 shows the CFLR bit assignments when it indicates a correctable TCM error Figure 4 53 CF...

Page 147: ...er characteristics are Purpose Reflects the build configuration options used to build the processor Usage constraints The Build Options 1 Register is a read only register accessible in Privileged mode only Configurations Available in all processor configurations Attributes See Table 4 56 on page 4 78 Figure 4 54 shows the Build Options 1 Register bit assignments Figure 4 54 Build Options 1 Registe...

Page 148: ...ter accessible in Privileged mode only Configurations Available in all processor configurations Attributes See Table 4 57 on page 4 79 Figure 4 55 shows the Build Options 2 Register bit assignments Figure 4 55 Build Options 2 Register bit assignments Table 4 56 Build Options 1 Register bit assignments Bits Name Function 31 12 TCM_HI_INIT_ADDR Default high address for the TCM 11 0 SBZ 31 25 24 23 2...

Page 149: ...rity logic 10 32 bit error detection and correction 11 64 bit error detection and correction 25 24 BTCM_ES Indicates whether an error scheme is implemented on the BTCM interface s 00 no error scheme 01 8 bit parity logic 10 32 bit error detection and correction 11 64 bit error detection and correction 23 NO_IE Indicates whether the processor supports big endian instructions 0 processor supports bi...

Page 150: ...ve port 0 processor contains an AXI slave port 1 processor does not contain an AXI slave port 8 7 ICACHE_ES Indicates whether an error scheme is implemented for the instruction cache 00 no error scheme 01 8 bit parity error detection 11 64 bit error detection and correction If the processor does not contain an Icache these bits are set to 00 6 5 DCACHE_ES Indicates whether an error scheme is imple...

Page 151: ...onjunction with the DPU uses program flow prediction to locate branches in the instruction stream and the strategies used to determine if a branch is likely to be taken or not It contains the following sections About the prefetch unit on page 5 2 Branch prediction on page 5 3 Return stack on page 5 5 Controlling instruction prefetch and program flow prediction on page 5 6 ...

Page 152: ...ta fetches in its FIFO There is an additional FIFO between the PFU and the DPU that can normally buffer up to eight instructions This reduces or eliminates stall cycles after a branch instruction This increases the performance of the processor Program flow prediction occurs in the PFU by predicting the outcome of conditional branches using the branch predictor and for direct branches calculating t...

Page 153: ...ddress is a fixed offset encoded in the instruction from the program counter If such an instruction is fetched and the program counter is known predicting the destination of the branch only involves predicting whether the instruction passes or fails its condition code that is whether the branch is taken or not taken 2 Indirect branches such as load and Branch and eXchange BX instructions that writ...

Page 154: ...anch predictor detects these cases and provides some hysteresis for the hint value For direct branches the target address is calculated statically from the instruction encoding and the program counter For indirect branches the hint value predicts if the branch is taken or not taken and the return stack can sometimes be used to predict the target address When the destination of a branch cannot be c...

Page 155: ...s onto the return stack The instructions that the PFU recognizes as procedure calls are in both the ARM and Thumb instruction sets BL immediate BLX immediate BLX Rm When the return stack detects a taken return instruction the PFU issues an instruction fetch from the location at the top of the return stack and pops the return stack The instructions that the PFU recognizes as procedure returns are i...

Page 156: ... page 4 40 The fetch rate predictor can be disabled by setting FRCDIC in the ACTLR When the predictor is disabled the PFU fetches instructions at the fastest rate possible The dynamic branch predictor is controlled with the BP field in the ACTLR In normal operation the branch prediction is taken from the global history table You can also force the prediction to be always taken or always not taken ...

Page 157: ...al Chapter 6 Events and Performance Monitor This chapter describes the Performance Monitoring Unit PMU and event bus interface It contains the following sections About the events on page 6 2 About the PMU on page 6 6 Performance monitoring registers on page 6 7 Event bus interface on page 6 19 ...

Page 158: ...l from the L2 memory system generates this event Accesses that do not cause a new cache refill but are satisfied from refilling data of a previous miss are not counted Where instruction fetches consist of multiple instructions these accesses count as single events CP15 cache maintenance operations do not count as events 0x01 1 Data cache miss Each data read from or write to normal cacheable memory...

Page 159: ... could have been predicted by the branch prediction resources of the processor 0x12 16 Stall because instruction buffer cannot deliver an instruction This can indicate an instruction cache miss This event occurs every cycle where the condition is present 0x40 17 Stall because of a data dependency between instructions This event occurs every cycle where the condition is present 0x41 18 Data cache w...

Page 160: ... instruction that did not initiate a linefill because of a resource shortage 0x56 N A Non cacheable access on AXI master bus 0x57 28 Instruction cache access This is an analog to event 0x04 0x58 N A Store buffer operation has detected that two slots have data in same cache line but with different attributes 0x59 29 Dual issue case A branch 0x5A 30 Dual issue case B1 B2 F2 load store F2D 0x5B 31 Du...

Page 161: ...correctable ECC error reported by prefetch unit Yes 0x6B 45 TCM fatal ECC error reported by AXI slave interface 0x6C 46 TCM correctable ECC error reported by AXI slave interface Yes 0x6D N A Cycle count 0xFF a This event is only generated for by revisions r1p2 and later of the processor Table 6 1 Event bus interface bit functions continued EVNTBUS bit position Description CFLR update Event Ref Val...

Page 162: ...nter is read or written The three Event Selection registers one per counter are read and written through one CP15 register in the same way Using the control registers you can enable or disable each of the event counters individually and read and reset the overflow flag for each counter Any or all of the counters can be enabled to assert an interrupt request output nPMUIRQ on overflow When the proc...

Page 163: ...ge 6 14 c9 Event Count Registers on page 6 15 c9 User Enable Register on page 6 15 c9 Interrupt Enable Set Register on page 6 16 c9 Interrupt Enable Clear Register on page 6 17 6 3 1 c9 Performance Monitor Control Register The PMCR Register characteristics are Purpose Controls the operation of the three count registers and the PMCCNTR Register Usage constraints The PMCR Register is a read write re...

Page 164: ...ortex R4 15 11 N Specifies the number of counters implemented 0x3 three counters implemented 10 6 RAZ on reads Should Be Zero or Preserved SBZP on writes 5 DP Disable PMCCNTR when prohibited that is when non invasive debug is not enabled 0 Count is enabled in prohibited regions This is the reset value 1 Count is disabled in prohibited regions 4 X Enable export of the events to the event bus for an...

Page 165: ... the corresponding counter is disabled Any enable that reads as 1 indicates the corresponding counter is enabled Writing a 1 to a particular count enable bit enables that counter Writing a 0 to a count enable bit has no effect You must use the PMCNTENCLR to disable the counters All counters are disabled at reset The PMCNTENSET Register retains its value when the enable bit of the PMCR is clear eve...

Page 166: ...pdated Any enable written with a value of 1 clears the counter enable You must use the Count Enable Set Register to enable the counters All counters are disabled at reset Writing to bits in this register disables individual counters and clears the corresponding bits in the PMCNTENSET Register see c9 Count Enable Set Register on page 6 8 You can use the enable EN bit 0 of the PMCR Register to disab...

Page 167: ...SR bit assignments To access the PMOVSR read or write CP15 with MRC p15 0 Rd c9 c12 3 Read PMOVSR MCR p15 0 Rd c9 c12 3 Write PMOVSR If an overflow flag is set to 1 in the PMOVSR it remains set until one of the following happens writing 1 to the flag bit in the PMOVSR clears the flag the processor is reset The following operations do not clear the overflow flags disabling the overflowed counter in...

Page 168: ... see c9 Event Type Selection Register on page 6 14 If you attempt to use the PMSWINC Register to increment an Event Count Register when the counter event is set to a value other than 0x00 the result is Unpredictable Configurations Available in all processor configurations Attributes See Table 6 6 Figure 6 5 shows the PMSWINC bit assignments Figure 6 5 PMSWINC Register bit assignments Table 6 6show...

Page 169: ...igurations Available in all processor configurations Attributes See Table 6 7 Figure 6 6 shows the PMSELR bit assignments Figure 6 6 PMSELR Register bit assignments Table 6 7 shows the PMSELR bit assignments Any values programmed in the PMSELR Register other than those specified in Table 6 7 are Unpredictable To access the PMSELR Register write CP15 with MCR p15 0 Rd c9 c12 5 Write PMSELR Register...

Page 170: ...ssor has three Event Type Select Registers PMXEVTYPER0 to PMXEVTYPER2 each corresponding to one of the Performance Monitor Count PMXEVCNTR Registers PMXEVCNTR0 to PMXEVCNTR2 The value in PMSELR determines access to these registers The PMXEVTYPER Register characteristics are Purpose Selects the events you want a PMXEVCNTR Register to count Usage constraints The PMXEVTYPER Register is A read write r...

Page 171: ... counts instances of an event selected by the corresponding PMXEVTYPER Register The value in PMSELR determines access to these registers Each PMXEVCNTR Register is A 32 bit read write register Accessible in Privileged mode User mode only when the PMUSERENR EN bit is set to 1 see c9 User Enable Register To access the current Event Count Registers read or write CP15 with MRC p15 0 Rd c9 c13 2 Read c...

Page 172: ...or write CP15 with MRC p15 0 Rd c9 c14 0 Read PMUSERENR Register MCR p15 0 Rd c9 c14 0 Write PMUSERENR Register 6 3 11 c9 Interrupt Enable Set Register The PMINTENSET Register characteristics are Purpose Determines if any of the PMXEVCNTR Registers PMXEVCNTR0 PMXEVCNTR2 and PMCCNTR generate an interrupt request on overflow Usage constraints The PMINTENSET Register is a read write register accessib...

Page 173: ...o an external interrupt controller for prioritization and masking This is the only mechanism that signals this interrupt to the processor Note ARM expects that the Performance Monitor interrupt request signal nPMUIRQ connects to a system interrupt controller 6 3 12 c9 Interrupt Enable Clear Register The PMINTENCLR Register characteristics are Purpose Determines if any of the PMXEVCNTR Registers PM...

Page 174: ... bit disables interrupt generation on overflow of that counter Writing a 0 has no effect You can only enable interrupt requests by writing to the PMINTENSET Register To access the PMINTENCLR Register read or write CP15 with MRC p15 0 Rd c9 c14 2 Read PMINTENCLR Register MCR p15 0 Rd c9 c14 2 Write PMINTENCLR Register C 31 3 2 1 0 Reserved P2 P1 P0 Performance monitor counter overflow interrupt dis...

Page 175: ... logic in the system for that purpose See Table 6 1 on page 6 2 to see which bit of the event bus each event is signaled on Note If an event is being counted in the PMU the count might not be incremented in exactly the same cycle that the event is signaled on the event bus 6 4 1 Use of the event bus and counters The event bus is designed to be connected to the ETM R4 that enables processor events ...

Page 176: ...emory Protection Unit This chapter describes the Memory Protection Unit MPU It contains the following sections About the MPU on page 7 2 Memory types on page 7 7 Region attributes on page 7 8 MPU interaction with memory system on page 7 9 MPU faults on page 7 10 MPU software accessible registers on page 7 11 ...

Page 177: ...c6 see MPU control and configuration on page 4 3 Memory region control read and write access is permitted only from Privileged modes Table 7 1 shows the default memory map Table 7 1 Default memory map Address range Instruction memory type Data memory type eXecute Never Instruction cache enabled Instruction cache disabled Data cache enabled Data cache disabled 0xFFFFFFFF Normal Non cacheable only i...

Page 178: ...gion enable Region base address The base address defines the start of the memory region You must align this to a region sized boundary For example if a region size of 8KB is programmed for a given region the base address must be a multiple of 8KB Note If the region is not aligned correctly this results in Unpredictable behavior Region size The region size is specified as a 5 bit value encoding a r...

Page 179: ... data read access can execute instructions For more information see the ARM Architecture Reference Manual For information about how to program access permissions see Table 4 36 on page 4 56 Instructions cannot be executed from regions with Device or Strongly ordered memory type attributes The processor treats such regions as if they have XN permissions 7 1 2 Overlapping regions You can program the...

Page 180: ...ck it uses a write access to region 2 by the processor causes the MPU to raise a permission fault Figure 7 2 Overlay for stack protection Example of using subregions You can use subregions for stack protection as shown in Figure 7 3 For example Allocate to region 1 the appropriate size for all stacks Set the least significant subregion disable bit That is set the subregion disable field bits 15 8 ...

Page 181: ...ccesses for an address that is not mapped to a region in the MPU generate a background fault You can override this behavior by programming region 0 as a 4GB background region In this way if the address does not fall into any of the other 11 regions the attributes and access permissions you specified for region 0 control the access In Privileged modes you can also override this behavior by setting ...

Page 182: ...to Normal memory In particular reads from Device memory must first drain the store buffer of all writes to Device memory all accesses to Strongly ordered memory must first drain the store buffer completely Similarly when it accesses Strongly ordered or Device type memory the processor s response to interrupts must be modified and the interrupt response latency is longer See Low interrupt latency o...

Page 183: ...cture the TEX C and B bits were known as the Type Extension Cacheable and Bufferable bits These names no longer adequately describe the function of the B C and TEX bits All memory attributes that are cacheable write back or write through are also implicitly read allocate Table 4 35 on page 4 56 shows which attributes are write allocate In addition the Region Access Control Registers contain the sh...

Page 184: ...the same as the attributes and permissions of the region in the default memory map that covers the code and that the region is executable in Privileged mode 2 Clean and invalidate the data caches 3 Disable caches 4 Invalidate the instruction cache The following code is an example of enabling the MPU MRC p15 0 R1 c1 c0 0 read CP15 register 1 ORR R1 R1 0x1 DSB MCR p15 0 R1 c1 c0 0 enable MPU ISB Fet...

Page 185: ... subregion of an MPU region A background fault does not occur if the background region is enabled and the access is Privileged See Background regions on page 7 6 7 5 2 Permission fault A permission fault is generated when a memory access does not meet the requirements of the permissions defined for the memory region that it accesses See Region access permissions on page 7 4 7 5 3 Alignment fault A...

Page 186: ...on Confidential 7 6 MPU software accessible registers Figure 4 2 on page 4 3 shows the CP15 registers that control the MPU When the MPU is not present the c6 MPU memory region programming registers on page 4 51 read as zero and ignore writes in Privileged mode No Undefined Instruction exceptions are taken ...

Page 187: ... one L1 memory system It contains the following sections About the L1 memory system on page 8 2 About the error detection and correction schemes on page 8 4 Fault handling on page 8 7 About the TCMs on page 8 13 About the caches on page 8 18 Internal exclusive monitor on page 8 34 Memory types and L1 memory system behavior on page 8 35 Error detection events on page 8 36 ...

Page 188: ...e can be configured at implementation time to have an error detection and correction scheme to protect the data stored in the memory from errors Each TCM interface also has support for logic external to the processor to tell the processor that an error has occurred The MPU handles accesses to both the instruction and data sides The MPU is responsible for protection checking address access permissi...

Page 189: ...ial Figure 8 1 L1 memory system block diagram AXI master Instruction cache controller and RAMs Data cache controller and RAMs B0TCM AXI bus AXI bus External Tightly Coupled Memory TCM AXI slave Data Processing Unit DPU Memory Protection Unit MPU Prefetch Unit PFU Load Store Unit LSU Interconnect ATCM B1TCM Processor ...

Page 190: ...s and disadvantages of each scheme to the implementer See Cache error detection and correction on page 8 20 for information about the operation of the error schemes for the caches and TCM internal error detection and correction on page 8 14 for the TCMs The error schemes are each described in terms of their operation on a doubleword 64 bits of data because this is the amount of data that the proce...

Page 191: ...an be detected per doubleword if there are two in each word 8 2 3 Read Modify Write The smallest unit of data that the processor can write is a byte However both the ECC schemes are computed on data chucks that are larger than this To write any data to a RAM protected with ECC requires the error code for that data to be recomputed and rewritten If the entire data chunk is not written for example a...

Page 192: ...xecuting the instruction that caused the read and reads the corrected data from the RAM if no more errors have occurred This takes more clock cycles at least nine in the event of an error but has the side effect of correcting the data in the RAM so that the errors in the data cannot become worse Note Because RAM errors generally occur infrequently the extra cycles required to perform correct and r...

Page 193: ...ty or ECC error TCM parity or ECC error TCM external error TCM external retry request Watchpoints Fault handling is described in Faults Fault status information on page 8 9 Correctable Fault Location Register on page 8 10 Usage models on page 8 10 8 3 1 Faults The classes of fault that can occur are MPU faults External faults on page 8 8 Cache and TCM parity and ECC errors on page 8 8 TCM external...

Page 194: ... corrected generates an abort Parity and ECC errors can only occur on reads although these reads might be a side effect of store instructions Aborts generated by loads are always synchronous Aborts generated by store instructions to the TCM are also always synchronous while those to the cache are always asynchronous These errors can also occur on some cache maintenance operations see Errors on cac...

Page 195: ...other types of exception See Exceptions on page 3 14 for more information This information can be used to resume program execution after the abort is handled Note When a prefetch abort has occurred ARM recommends that you do not use the link register value for determining the aborting address because 32 bit Thumb instructions do not have to be word aligned and can cause an abort on either halfword...

Page 196: ...che The effect of debug events on these registers is described in Debug exception on page 12 44 8 3 3 Correctable Fault Location Register Correctable faults are normally automatically corrected by the processor but depending on the configuration and on the access that generated the fault an exception might not be generated and the fault status registers might not be updated In all cases informatio...

Page 197: ...oller When such an event occurs the interrupt input to the processor is set and the processor takes an interrupt exception When your interrupt handler has identified the source of the interrupt as a correctable error it can read the CFLR to determine where the ECC error occurred You can examine this information to identify trends in such errors By masking the interrupt when necessary your software...

Page 198: ...r is in debug halt state any correctable error is corrected as appropriate but the memory access is not repeated to fetch the correct data therefore the instruction generating the error does not complete successfully Instead the sticky synchronous abort flag in the DBGDSCR is set See CP14 c1 Debug Status and Control Register on page 12 14 ...

Page 199: ...ace has a dedicated base address that you can place anywhere in the physical address map and must not be backed by memory implemented externally The ATCM and BTCM interfaces must have separate base addresses and must not overlap This section describes TCM attributes and permissions ATCM and BTCM configuration on page 8 14 TCM internal error detection and correction on page 8 14 TCM arbitration on ...

Page 200: ...M internal error detection and correction The size of each TCM interface is configured during integration The permissible TCM sizes are 0KB 4KB 8KB 16KB 32KB 64KB 128KB 256KB 512KB 1MB 2MB 4MB 8MB If the BTCM interface has two ports the size of the RAM attached to each port is half the total size for the BTCM interface The size of the TCM interfaces is visible to software in the TCM Region Registe...

Page 201: ...e error that is a 1 bit ECC error is detected on a TCM read made by the AXI slave interface the processor corrects the data inline before returning to the system When a correctable ECC error is detected on a TCM read made by the instruction side or data side the processor normally generates the correct data and writes it back to the TCM In the meantime the processor retries the read to fetch the c...

Page 202: ...ides information about whether the access results from an instruction fetch from the PFU a data access from the LSU or a DMA transfer from the AXI slave interface Each TCM port can also be configured to have an associated parity bit computed from the address and control signals for that port Read data and associated error code or parity bits are read back from the TCM port In addition the TCM memo...

Page 203: ...XI slave interfaces for TCMs The processor has a 64 bit AXI slave interface that provides access to the TCM interfaces from the AXI bus This interface is included by default but can be excluded during configuration of the processor You can use the slave interface for access to the TCM memories This also enables you to construct a system with a consistent view of memory That is the TCMs can be avai...

Page 204: ...urned when it is fetched without waiting for the linefill to complete that is the caches also support streaming If an error is reported to the L2 memory interface for a linefill the linefill does not update the cache RAMs but an abort is only generated if the error was reported on the critical word If all the cache lines in a set are valid to allocate a different address to the cache the cache con...

Page 205: ...write access is performed on the AXI master interface For write back write allocate stores that miss in the data cache a linefill is started using either of the two linefill buffers When the linefill data is returned from the L2 memory system the data in the store buffer is merged into the linefill buffer to be subsequently written into the cache Store buffer draining A store buffer entry is drain...

Page 206: ...che maintenance operations on page 8 23 Error build options The caches can detect and correct errors depending on the build options used in the implementation The build options for the instruction cache can be different to the data cache If the parity build option is enabled the cache is protected by parity bits For both the instruction and data cache the data RAMs include one parity bit per byte ...

Page 207: ...dating the cache line that contains the parity error The processor automatically performs this invalidation when an error is detected The correct data can then be re read from the L2 memory system Parity aborts If aborts on parity errors are enabled software is notified of the error by a data abort or prefetch abort The error is still automatically corrected by the hardware even if an abort is gen...

Page 208: ...cted that such a situation can be fatal to the software process running If one of the force write though settings is enabled memory marked as write back write allocate behaves as write though This ensures that cache lines can never be dirty therefore the error can always be recovered from by invalidating the cache line that contains the ECC error All detectable errors in the instruction cache can ...

Page 209: ...the L2 memory interface so data is not lost and the error is not fatal Errors on evictions If the cache controller has determined a cache miss has occurred it might have to do an eviction before a linefill can take place This can occur on reads and on writes if write allocation is enabled for the region Certain cache maintenance operations also generate evictions If it is a data cache line that is...

Page 210: ...a cache lookup Any correctable errors found in the set that was looked up are fixed and if the address in question is found in the set it is invalidated Any uncorrectable errors cause an asynchronous abort An asynchronous abort can also be raised on a correctable error if aborts on RAM errors are enabled in the ACTLR Any detected error is signaled with the appropriate event Invalidate data cache b...

Page 211: ...ed with the appropriate event Clean and invalidate data cache by address This operation requires a cache lookup Any correctable errors found in the set that was looked up are fixed and if the address in question is found in the set the instruction carries on with the clean and invalidate operation When the tag lookup is done the dirty RAM is checked Note When force write through is enabled the dir...

Page 212: ...M on page 8 27 Tag RAM The tag RAMs consist of four ways of up to 512 lines The width of the RAM depends on the build options selected and the size of the cache The following tables show the tag RAM bits Table 8 4 shows the tag RAM bits when parity is implemented Table 8 5 shows the tag RAM bits when ECC is implemented Table 8 6 shows the tag RAM bits when neither parity nor ECC is implemented A c...

Page 213: ... the ECC code bits are also written The dirty RAM is bit enabled Table 8 8 shows the organization of a dirty RAM line Data RAM Data RAM is organized as eight banks of 32 bit wide lines or in the instruction cache as four banks of 64 bit wide lines This RAM organization means that it is possible to Perform a cache look up with one RAM access all banks selected together This is done for nonsequentia...

Page 214: ...y implemented on page 8 29 Data RAM sizes with ECC implemented on page 8 30 RAM address 0 1 2 3 Way 1 Word 6 Bank 0 Way 1 Word 7 Way 2 Word 4 Way 2 Word 5 Way 3 Word 2 Way 3 Word 3 Way 0 Word 0 Way 0 Word 1 Bank 1 Way 2 Word 6 Bank 2 Way 2 Word 7 Way 3 Word 4 Way 3 Word 5 Way 0 Word 2 Way 0 Word 3 Way 1 Word 0 Way 1 Word 1 Bank 3 Way 3 Word 6 Bank 4 Way 3 Word 7 Way 0 Word 4 Way 0 Word 5 Way 1 Wor...

Page 215: ... 4KB ways 4 banks 64 bits 512 lines or 8 banks 32 bits 512 lines 32KB 4 8KB ways 4 banks 64 bits 1024 lines or 8 banks 32 bits 1024 lines 64KB 4 16KB ways 4 banks 64 bits 2048 lines or 8 banks 32 bits 2048 lines Table 8 10 Data cache data RAM sizes no parity or ECC Cache size Data RAMs 4KB 4 1KB ways 8 banks 32 bits 128 lines 8KB 4 2KB ways 8 banks 32 bits 256 lines 16KB 4 4KB ways 8 banks 32 bits...

Page 216: ...M sizes with parity Cache size Data RAMs 4KB 4 1KB ways 8 banks 36 bits 128 lines 8KB 4 2KB ways 8 banks 36 bits 256 lines 16KB 4 4KB ways 8 banks 36 bits 512 lines 32KB 4 8KB ways 8 banks 36 bits 1024 lines 64KB 4 16KB ways 8 banks 36 bits 2048 lines Table 8 13 Data cache RAM bits with parity RAM bits Description Bit 35 Parity bit for byte 31 24 Bit 34 Parity bit for byte 23 16 Bit 33 Parity bit ...

Page 217: ...ata cache if L2 memory might have changed since the cache was disabled Before enabling the instruction cache you must invalidate the entire instruction cache if L2 memory might have changed since the cache was disabled See Enabling or disabling AXI slave accesses on page 9 23 and Accessing RAMs using the AXI slave interface on page 9 24 for information about how to access the cache RAMs using the ...

Page 218: ...e The following code is an example of enabling the data cache MRC p15 0 R1 c1 c0 0 Read SCTLR configuration data ORR R1 R1 0x1 2 DSB MCR p15 0 r0 c15 c5 0 Invalidate entire data cache MCR p15 0 R1 c1 c0 0 enabled data cache The following code is an example of disabling the cache RAMs MRC p15 0 r1 c1 c0 0 Read SCTLR configuration data BIC r1 r1 0x1 2 DSB MCR p15 0 r1 c1 c0 0 disabled data cache Cle...

Page 219: ...ta cache has no dirty data for example if the cache has not been enabled yet MRC p15 0 r1 c1 c0 1 Read ACTLR Change bits 5 3 as required MCR p15 0 r1 c1 c0 1 Write ACTLR MCR p15 0 r0 c15 c5 0 Invalidate entire data cache MCR p15 0 r0 c7 c5 0 Invalidate entire instruction cache MRC p15 0 r0 c1 c0 0 Read SCTLR ORR r0 r0 0x1 2 Enable data cache bit ORR r0 r0 0x1 12 Enable instruction cache bit DSB MC...

Page 220: ...rent processors See the ARM Architecture Reference Manual for more information about how these instructions work When a load exclusive access is performed the internal exclusive monitor moves to the exclusive state It moves back to the open state when a store exclusive access or clear exclusive instruction is performed The internal exclusive monitor holds exclusivity state for the Cortex R4 proces...

Page 221: ...pts on page 3 16 for more information about interrupt behavior Only the internal exclusive monitor is used for exclusive accesses to Non shared memory Exclusive accesses to shared memory are checked using the internal monitor and also if necessary any external monitor using the L2 memory interface Accesses resulting from SWP and SWPB instructions to Normal non shared memory are not marked as locke...

Page 222: ...a returned as if no external error had been signaled The processor centric TCM events are only signaled for errors in data that would have otherwise been used by the processor Errors on purely speculative reads never generate these errors They consist of fatal and correctable events for the prefetch unit to signal errors on instruction fetches the load store unit to signal errors on data accesses ...

Page 223: ...s reserved 8 37 ID073015 Non Confidential generates an event See Table 6 1 on page 6 2 to see which events are CFLR related For correctable cache errors the CLFR does not record whether the error occurred in the data RAM or tag dirty RAM This distinction is only made by the events ...

Page 224: ...he Level two L2 interface not covered in the AMBA AXI Protocol Specification It contains the following sections About the L2 interface on page 9 2 AXI master interface on page 9 3 AXI master interface transfers on page 9 7 AXI slave interface on page 9 20 Enabling or disabling AXI slave accesses on page 9 23 Accessing RAMs using the AXI slave interface on page 9 24 ...

Page 225: ...I slave interfaces The processor is designed for use in larger chip designs using the AMBA AXI protocol The processor uses the L2 interfaces as its interface to memory and peripheral devices External AXI masters that can include the processor itself can use the AXI slave interface to access the processor RAMs You can use the AXI slave interface for DMA access into and out of the TCMs or to perform...

Page 226: ...stem that is connected to the Cortex R4 AXI master port This might not be the Cortex R4 AXI slave port The following sections describe the attributes of the AXI master interface and provide information about the types of burst generated Identifiers for AXI bus accesses on page 9 4 Write response on page 9 4 Linefill buffers and the AXI master interface on page 9 4 Eviction buffer on page 9 5 Memor...

Page 227: ...th the same ID before the target accepts the data of the first write Note The AXI master does not generate two outstanding read accesses with the same ID The AXI master does not interleave write data from two different bursts even if the bursts have different IDs 9 2 2 Write response The AXI master requires that the slave does not return a write response until it has received both the write data a...

Page 228: ...ace These are generated from the memory type and outer region attributes Table 9 3 shows the encodings the master interface uses for the ARUSERM and AWUSERM signals These are generated from the memory type and inner region attributes Table 9 2 ARCACHEM and AWCACHEM encodings Encodinga a Encodings not shown in the table are reserved Meaning b0000 Strongly ordered b0001 Device b0011 Non cacheable b0...

Page 229: ...ory address that is marked as either Cacheable write back read and write allocate non shared Cacheable write through read allocate only non shared However Device and Strongly ordered memory is always Non cacheable Also any unaligned access to Device or Strongly ordered memory generates an alignment fault and therefore does not cause any AXI transfer This means that the access examples given in thi...

Page 230: ... infer any additional restrictions from the example tables given Restrictions described here are applicable to the r1p0 r1p1 and r1p2 revisions of the processor and might not be true for future revisions Load and store instructions to Non cacheable memory might not result in an AXI transfer because the data might either be retrieved from or merged into the internal store data buffers The exception...

Page 231: ...re always a 64 bit transfer size and never locked or exclusive Transactions to Device and Strongly ordered memory are always to addresses that are aligned for the transfer size See Strongly ordered and Device transactions Exclusive and Locked accesses are always to addresses that are aligned for the transfer size Write data is never interleaved In addition there are various limitations to the ID v...

Page 232: ...ongly ordered or Device memory addresses 0x1 0x2 0x3 0x5 0x6 or 0x7 generates an alignment fault 0x4 byte 4 0x04 Incr 8 bit 1 data transfer 0x5 byte 5 0x05 Incr 8 bit 1 data transfer 0x6 byte 6 0x06 Incr 8 bit 1 data transfer 0x7 byte 7 0x07 Incr 8 bit 1 data transfer Table 9 5 LDRH from Strongly ordered or Device memory Address 3 0 ARADDRM ARBURSTM ARSIZEM ARLENM 0x0 halfword 0 0x00 Incr 16 bit 1...

Page 233: ...ers five registers an LDM5 in Strongly ordered or Device memory Note A load multiple from address 0x1 0x2 0x3 0x5 0x6 0x7 0x9 0xA 0xB 0xD 0xE or 0xF generates an alignment fault Table 9 7 LDM5 Strongly ordered or Device memory Address 4 0 ARADDRM ARBURSTM ARSIZEM ARLENM 0x00 word 0 0x00 Incr 32 bit 5 data transfers 0x04 word 1 0x04 Incr 32 bit 5 data transfers 0x08 word 2 0x08 Incr 32 bit 5 data t...

Page 234: ...RM AWBURSTM AWSIZEM AWLENM WSTRBM 0x00 byte 0 0x00 Incr 8 bit 1 data transfer b00000001 0x01 byte 1 0x01 Incr 8 bit 1 data transfer b00000010 0x02 byte 2 0x02 Incr 8 bit 1 data transfer b00000100 0x03 byte 3 0x03 Incr 8 bit 1 data transfer b00001000 0x04 byte 4 0x04 Incr 8 bit 1 data transfer b00010000 0x05 byte 5 0x05 Incr 8 bit 1 data transfer b00100000 0x06 byte 6 0x06 Incr 8 bit 1 data transfe...

Page 235: ...e values of AWADDRM AWBURSTM AWSIZEM and AWLENM for an STM that writes seven registers an STM7 over the AXI master port to Strongly ordered or Device memory Note A store multiple to address 0x1 0x2 0x3 0x5 0x6 or 0x7 generates an alignment fault Table 9 10 STR or STM1 to Strongly ordered or Device memory Address 2 0 AWADDRM AWBURSTM AWSIZEM AWLENM WSTRBM 0x0 word0 0x00 Incr 32 bit 1 data transfer ...

Page 236: ...ructions accessing various addresses in Non cacheable Normal memory They are provided as examples only and are not an exhaustive description of the AXI transactions Depending on the state of the processor and the timing of the accesses the actual bursts generated might have a different size and length to the examples shown even for the same instruction Table 9 14 shows possible values of ARADDRM A...

Page 237: ... transfer 0x1 byte 1 0x01 Incr 64 bit 1 data transfer 0x2 byte 2 0x00 Incr 64 bit 1 data transfer 0x3 byte 3 0x00 Incr 64 bit 2 data transfers 0x4 byte 4 word 1 0x04 Incr 32 bit 1 data transfer 0x5 byte 5 0x05 Incr 32 bit 2 data transfers 0x6 byte 6 0x06 Incr 16 bit 1 data transfer 0x08 Incr 16 bit 1 data transfer 0x7 byte 7 0x04 Incr 32 bit 2 data transfers Table 9 16 LDM5 Non cacheable Normal me...

Page 238: ... addition write operations to Normal memory can be merged to create more complex AXI transactions See Normal write merging on page 9 17 for examples Table 9 17 shows possible values of AWADDRM AWBURSTM AWSIZEM and AWLENM for an STRH to Normal memory 0x18 word 6 0x18 Incr 64 bit 1 data transfer 0x00 Incr 64 bit 2 data transfers 0x1C word 7 0x1C Incr 32 bit 1 data transfer 0x00 Incr 64 bit 2 data tr...

Page 239: ...six words from memory The number of AXI transactions generated by this instruction depends on the base address R10 If all six words are in the same cache line there is a single AXI transaction For example for LDMIA R10 R0 R5 with R10 0x1008 the interface might generate a burst of three 64 bit read transfers as shown in Table 9 19 Table 9 18 STR or STM1 to cacheable write through or Non cacheable N...

Page 240: ...on into a single write burst to improve the efficiency of the AXI port If the AXI master receives several write requests that do not form a single contiguous burst it can choose to output a single burst with the WSTRBW signal low for the bytes that do not have any data For write accesses to Normal memory the STB can perform writes out of order if there are no address dependencies It can do this to...

Page 241: ...ed the STRB and STRH writes into one buffer entry and therefore a single AXI transfer the fourth in the burst The writes that occupy three buffer entries have been merged into a single AXI burst of four transfers The write generated by the STR instruction has not occurred because it was overwritten by the STM instruction The write transfers have occurred out of order with respect to the original p...

Page 242: ...the AXI transactions Depending on the state of the processor and the timing of the accesses the actual bursts generated might have a different size and length to the examples shown even for the same instruction If the same memory is marked as write back cacheable and the addresses are allocated into a cache line no AXI write transactions occur until the cache line is evicted and performs a write b...

Page 243: ...f the access gains access on the second cycle when the LSU is using the other port and can continue in lock step with the LSU assuming both are accessing sequential data Accesses to the ATCM are more likely to encounter a conflict because there is only one port on the interface Memory BIST ports are routed through the AXI slave interface logic to access the RAMs Memory BIST access is assumed only ...

Page 244: ...M port the AXI slave returns a SLVERR response to the AXI transaction The AXI slave ignores late error and retry responses from the TCM 9 4 4 Cache parity and ECC support When the caches support parity or ECC the AXI slave interface can read and write the parity or ECC code bits directly No errors are detected automatically and on writes the AXI slave does not automatically generate the correct pa...

Page 245: ... used Memory type and cacheability so AxCACHE is not used Atomic accesses The AXI slave accepts locked transactions but makes no use of the locking information that is AxLOCK The AXI slave interface has no exclusive access monitor If there are any exclusive accesses the AXI slave interface responds with an OKAY response The width of the ID signals for the AXI slave port is 8 bits You must avoid bu...

Page 246: ...d ACTLR ORR R1 R1 0x1 24 DSB MCR p15 0 R1 c1 c0 1 enabled AXI slave accesses to the cache RAMs ISB Clean entire data cache This routine depends on the data cache size It can be omitted if it is known that the data cache has no dirty data Fetch from uncached memory Fetch from uncached memory Fetch from uncached memory Fetch from uncached memory The following code is an example of disabling AXI slav...

Page 247: ...a one hot 4 bit input with each bit corresponding to a particular RAM or group of RAMs For the caches and the BTCMs more decoding is performed depending on the address of the request ARADDRS for reads and AWADDRS for writes For more information see TCM RAM access on page 9 25 Cache RAM access on page 9 26 Note Because AWUSERS and AWADDRS work in the same way as ARUSERS and ARADDRS the following se...

Page 248: ...indicates the address of the doubleword within the TCM that you want to access If you are accessing a TCM that is smaller than the maximum 8MB then it is possible to address a doubleword that is outside of the physical size of the TCM An access to the TCM RAMs is given a SLVERR error response if It is outside the physical size of the targeted TCM RAM that is bits of ARADDRS 22 MSB 1 are non zero T...

Page 249: ...truction caches have the same format Because the instruction cache does not have a dirty RAM accesses to it generate the SLVERR error response Table 9 29 Table 9 30 and Table 9 31 on page 9 27 show the chip select decodes for selecting the cache RAMs in the processor Table 9 29 Cache RAM chip select decode Inputs RAM selected ARUSERS 3 0 ARADDRS 22 19 0100 0000 Instruction cache data RAM 0100 0001...

Page 250: ...st write to a multiple of 64 bits of data Therefore for 32 bit transfers fixed bursts are not permitted and the number of transfers per transaction must be even that is if AWSIZES 2 AWBURSTS must not be 0 and AWLENS must be odd Data RAM access The following tables shows the data formats for cache data RAM accesses Table 9 32 on page 9 28 shows the format when neither parity nor ECC is implemented ...

Page 251: ... 16 or 55 48 47 32 Data value 31 16 or 63 48 31 18 Not used read as zero 17 Parity bit for data value 15 8 or 47 40 16 Parity bit for data value 7 0 or 39 32 15 0 Data value 15 0 or 47 32 Table 9 34 Data format instruction cache with ECC Data bit Description 63 52 Not used read as zero 51 48 Upper or lower half of the ECC 64 codea a If accessing bits 31 16 of the data bits 51 48 hold the lower hal...

Page 252: ...mat for write accesses when parity is implemented Table 9 41 on page 9 31 shows the format for write accesses when ECC is implemented Table 9 35 Data format data cache with ECC Data bit Description 63 55 Not used read as zero 54 48 ECC 32 codea 47 32 Data value 31 16 or 63 48 31 23 Not used read as zero 22 16 ECC 32 code 15 0 Data value 15 0 or 47 32 a For a 64 bit access the ECC bits are duplicat...

Page 253: ...0 1 Table 9 38 Tag register format for reads with ECC Data bit Description 63 62 Not used read as zero 61 55 ECC way 2 3 54 Valid way 2 3 53 32 Tag value way 2 3 31 30 Not used read as zero 29 23 ECC way 0 1 22 Valid way 0 1 21 0 Tag value way 0 1 Table 9 39 Tag register format for writes no parity or ECC Data bit Description 63 23 Not used read as zero 22 Valid all ways 21 0 Tag value all ways Ta...

Page 254: ...data bus are used If two tag RAMs are written at the same time they are both written with the same data To write only one tag RAM using the AXI Slave select only one RAM with bits 18 15 of the address bus Table 9 41 Tag register format for writes with ECC Data bit Description 63 30 Not used read as zero 29 23 ECC all ways 22 Valid all ways 21 0 Tag value all ways ...

Page 255: ...re parity protection Table 9 42 Dirty register format with parity or with no error scheme Data bit Description 63 27 Not used read as zero 26 25 Outer attributes way 3 24 Dirty value way 3 23 19 Not used read as zero 18 17 Outer attributes way 2 16 Dirty value way 2 15 11 Not used read as zero 10 9 Outer attributes way 1 8 Dirty value way 1 7 3 Not used read as zero 2 1 Outer attributes way 0 0 Di...

Page 256: ... all dirty RAM banks use ARADDRS 18 15 4 b1111 The write must still be a word or doubleword write with all write strobes set ARADDRSm 18 15 determines which data is written If you break these rules for example if you access tag RAM banks 0 and 1 no SLVERR response is generated and any attempt to read or write banks in other combinations or multiple banks of other RAMs is Unpredictable Note If you ...

Page 257: ...imited All rights reserved 10 1 ID073015 Non Confidential Chapter 10 Power Control This chapter describes the processor power control functions It contains the following sections About power control on page 10 2 Power management on page 10 3 ...

Page 258: ...and return prediction reducing the number of incorrect instruction fetch and decode operations the caches use sequential access information to reduce the number of accesses to the tag RAMs and to unwanted data RAMs In the processor extensive use is also made of gated clocks and gates to disable inputs to unused functional blocks Only the logic actively in use to perform a calculation consumes any ...

Page 259: ...the entry into the Standby mode does not affect the memory system the WFI automatically performs a Data Synchronization Barrier operation This ensures that all explicit memory accesses occur in program order before the WFI has completed Systems using the VIC interface must ensure that the VIC is not masking any interrupts that are required for restarting the processor when in this mode of operatio...

Page 260: ...munication to the Power Management Controller You can use a Power Management Controller PMC to control the powering up and powering down of the processor The communication mechanism between the processor and the PMC is a memory mapped controller that is accessed by the processor performing Strongly ordered accesses to it The STANDBYWFI signal from the processor informs the PMC of the powerdown mod...

Page 261: ...U The Cortex R4F processor is a Cortex R4 processor that includes the optional FPU In this chapter the generic term processor means only the Cortex R4F processor This chapter contains the following sections About the FPU programmers model on page 11 2 General purpose registers on page 11 3 System registers on page 11 4 Modes of operation on page 11 11 Compliance with the IEEE 754 standard on page ...

Page 262: ...The FPU supports all data processing instructions and data types in the VFPv3 architecture as described in the ARM Architecture Reference Manual The FPU fully supports single precision and double precision add subtract multiply divide multiply and accumulate and square root operations It also provides conversions between fixed point and floating point data formats and floating point constant instr...

Page 263: ... 11 2 1 FPU views of the register bank In the FPU you can view the register bank as Sixteen 64 bit doubleword registers D0 D15 Thirty two 32 bit single word registers S0 S31 A combination of 64 bit and 32 bit registers from these views Figure 11 1 FPU register bank The mapping between the registers is as follows S 2n maps to the least significant half of D n S 2n 1 maps to the most significant hal...

Page 264: ...efined Instruction exception For a VFP system register to be accessible it must follow the rules in Table 11 2 and the VFP must also be accessible according to the CPACR See c1 Coprocessor Access Register on page 4 46 for more information Table 11 1 VFP system registers Register FMXR FMRX reg field Access type Reset state Floating Point System ID Register FPSID b0000 Read only 0x4102314xa Floating...

Page 265: ...n page 11 8 11 3 1 Floating Point System ID Register The FPSID Register characteristics are Purpose Indicates which VFP implementation is being used Usage constraints The FPSID Register is a read only register must be accessed in Privileged mode only Configurations Use this register if the device is configured as a Cortex R4F processor Attributes See Table 11 3 Figure 11 2 shows the FPSID bit assi...

Page 266: ...in future systems Configurations Use this register if the device is configured as a Cortex R4F processor Attributes See Table 11 4 on page 11 7 Figure 11 3 shows the FPSCR bit assignments Figure 11 3 FPSCR Register bit assignments 15 8 Part number 0x31 Cortex R4F 7 4 Variant 0x4 Cortex R4F 3 0 Revision When the build configuration includes the floating point unit this register identifies the revis...

Page 267: ...mode enabled 24 FZ Flush to zero mode enable bit 0 flush to zero mode disabled this is the reset value 1 flush to zero mode enabled 23 22 RMODE Rounding mode control field b00 round to nearest RN mode this is the reset value b01 round towards plus infinity RP mode b10 round towards minus infinity RM mode b11 round towards zero RZ mode 21 20 STRIDE Indicates the vector stride the reset value is 0x0...

Page 268: ...edia and VFP Feature Registers MVFR0 and MVFR1 The MVFR0 and MVFR1 Register characteristics are Purpose Describes the features supported by the FPU Usage constraints The MVFR0 and MVFR1 Registers are read only registers are accessible in Privileged modes only ARM recommends that any software attempting to determine the presence or absence of double precision floating point hardware support uses th...

Page 269: ...bit assignments Bits Name Function 31 28 RM All VFP rounding modes supported 0x1 27 24 SV VFP short vector unsupported 0x0 23 20 SR VFP hardware square root supported 0x1 19 16 D VFP hardware divide supported 0x1 15 12 TE Only untrapped exception handling can be selected 0x0 11 8 DP Double precision supported in VFPv3 0x2 7 4 SP Single precision supported in VFPv3 0x2 3 0 RB 16x64 bit media regist...

Page 270: ...d 11 10 ID073015 Non Confidential 11 8 LS Load and store instructions supported for VFP 0b0000 not supported 7 4 DN Propagation of NaN values supported for VFP 0x1 3 0 FZ Full denormal arithmetic supported for VFP 0x1 Table 11 7 MVFR1 Register bit assignments continued Bits Name Function ...

Page 271: ...lt from a zero operand are signaled appropriately VABS VNEG and VMOV are not considered arithmetic CDP operations and are not affected by flush to zero mode A result that is tiny as described in the IEEE 754 standard for the destination precision is smaller in magnitude than the minimum normal value before rounding and is replaced with a zero The IDC flag FPSCR 7 indicates when an input flush occu...

Page 272: ...ementation choices Some of the implementation choices permitted by the IEEE 754 standard and used in the VFPv3 architecture are described in the ARM Architecture Reference Manual NaN handling All single precision and double precision values with the maximum exponent field value and a nonzero fraction field are valid NaNs A most significant fraction bit of zero indicates a Signaling NaN SNaN A one ...

Page 273: ...ero mode results that are tiny before rounding as described in the IEEE 754 standard are flushed to a zero and the UFC flag FPSCR 3 is set See the ARM Architecture Reference Manual for information on flush to zero mode When the FPU is not in flush to zero mode operations are performed on subnormal operands If the operation does not produce a tiny result it returns the computed result and the UFC f...

Page 274: ... support user mode traps The exception enable bits in the FPSCR read as zero and cannot be written The processor also has six output pins FPIXC FPUFC FPOFC FPDZC FPIDC and FPIOC that each reflect the status of one of the cumulative exception flags See FPU signals on page A 23 for a description of these outputs You can mask each of these outputs masked by setting the corresponding bit in the Second...

Page 275: ... contains the following sections Debug systems on page 12 2 About the debug unit on page 12 3 Debug register interface on page 12 5 Debug register descriptions on page 12 10 Management registers on page 12 35 Debug events on page 12 42 Debug exception on page 12 44 Debug state on page 12 47 Cache debug on page 12 53 External debug interface on page 12 54 Using the debug functionality on page 12 57...

Page 276: ... a memory address 12 1 2 Protocol converter The debug host connects to the processor development system using an interface such as Ethernet The messages broadcast over this connection must be converted to the interface signals of the debug target A protocol converter performs this function for example RealView ICE 12 1 3 Debug target The debug target is the lowest level of the system An example of...

Page 277: ...ocessor debug unit is in Monitor debug mode the processor takes a debug exception instead of halting A special piece of software a monitor target can then take control to examine or alter the processor state Monitor debug mode is essential in real time systems where the processor cannot be halted to collect information Examples of these systems are engine controllers and servo mechanisms in hard d...

Page 278: ...ial data address comparators for triggering watchpoints see Watchpoint Value Registers on page 12 27 and Watchpoint Control Registers on page 12 28 a bidirectional Debug Communication Channel DCC see Debug communications channel on page 12 58 all other state information associated with the debug unit ...

Page 279: ...egisters that you can access through a coprocessor interface This is important for boot strap access to the register file It enables software running on the processor to identify the debug architecture version that the device implements 12 3 2 CP14 access permissions By default you can access all CP14 debug registers from a nonprivileged mode However you can program the processor to disable user m...

Page 280: ... CP14 c0 Debug Self Address Offset Register on page 12 13 MRC p14 0 Rd c0 c5 0 STC p14 c5 addressing mode DBGDTRRX Host to Target Data Transfer Register See Data Transfer Register on page 12 18 MCR p14 0 Rd c0 c5 0 LDC p14 c5 addressing mode DBGDTRTX Target to Host Data Transfer Register See Data Transfer Register on page 12 18 MRC p14 0 Rd c0 c1 0 MRC p14 0 PC c0 c1 0 DBGDSCR Debug Status and Con...

Page 281: ...04 c111 R RAZ 0x1C0 0x1DC c112 c119 RW DBGWCR Watchpoint Control Registers on page 12 28 0x1E0 0x1FC c120 c127 R RAZ 0x200 0x2FC c128 c191 R RAZ 0x300 c192 R DBGOSLAR Not implemented in this processor Reads as zero 0x304 c193 R DBGOSLSR Operating System Lock Status Register on page 12 30 0x308 c194 R DBGOSSRR Not implemented in this processor Reads as zero 0x30C c195 R RAZ 0x310 c196 RW DBGPRCR De...

Page 282: ...te without affecting the state of the remainder of the processor logic 12 3 8 APB port access permissions The restrictions for accessing the APB slave port are described as follows Privilege of memory access You must configure the system to disable accesses to the memory mapped registers based on the privilege of the memory access Power down The processor only supports a single power domain theref...

Page 283: ...r more information see Lock Access Register on page 12 38 OS Lock The processor does not support OS Lock Note These locks are set to their reset values only on reset of the debug logic provided by PRESETDBGn You must set the PADDRDBG31 input signal to 1 for accesses originated from the external debugger for the Software Lock override feature to work Table 12 4 External debug interface access permi...

Page 284: ...d W Write only This bit cannot be read Reads return an Unpredictable value RW Read or write RAZ Read As Zero Always zero when read RAO Read As One Always one when read SBZP Should Be Zero SBZ or Preserved P Must be written as 0 or preserved by writing the same value previously read from the same fields on the same processor These bits are usually reserved for future expansion UNP A read from this ...

Page 285: ... DBGDIDR 7 4 is the same as CP15 c0 bits 23 20 See c0 Main ID Register on page 4 14 for more information of CP15 c0 MIDR Reserved WRP 31 28 27 24 23 20 19 16 15 4 3 0 BRP Context ID Variant Revision Debug architecture version 8 7 Table 12 7 DBGDIDR Register bit assignments Bits Name Function 31 28 WRP Number of Watchpoint Register Pairs b0000 1 WRP b0001 2 WRPs b0111 8 WRPs 27 24 BRP Number of Bre...

Page 286: ...s read in this register during integration using the DBGROMADDR 31 12 and DBGROMADDRV inputs DBGROMADDRV must be tied off to 1 if DBGROMADDR 31 12 is tied off to a valid value Usage constraints The DBGDRAR Register is in CP14 c0 sub register c1 a 32 bit read only register accessible in User and Privileged modes Configurations Available in all processor configurations Attributes See Table 12 8 Figu...

Page 287: ...9 shows the DBGDSAR bit assignments You can configure the address read in this register during integration using the DBGSELFADDR 31 12 and DBGSELFADDRV inputs DBGSELFADDRV must be tied off to 1 if DBGSELFADDR 31 12 is tied off to a valid value To use the DBGDSAR Register read CP14 c0 with MRC p14 0 Rd c2 c0 0 Read DBGDSAR Register Debug bus self address offset value Reserved Valid bits 31 12 11 2 ...

Page 288: ...ved Reserved Reserved DTRTXfull l DTRRXfull l Table 12 10 DBGDSCR Register bit assignments Bits Name Function 31 RAZ on reads SBZP on writes 30 DTRRXfull The DTRRXfull flag 0 Read DTR DBGDTRRX is empty This is the reset value 1 Read DTR DBGDTRRX is full When set this flag indicates to the processor that there is data available to read from the DBGDTRRX It is automatically set on writes to the DBGD...

Page 289: ...is set to 1 when the processor pipeline retires one instruction It is cleared by a write to DBGDRCR 3 0 no instruction has completed execution since the last time this bit was cleared 1 an instruction has completed execution since the last time this bit was cleared 24 InstrCompl_l The latched instruction complete read only bit This flag determines whether the processor has completed execution of a...

Page 290: ... is set and an DBGITR write succeeds the processor fetches an instruction from the DBGITR for execution If this bit is set to 1 when the processor is not in debug state the behavior of the processor is Unpredictable 12 Comms CP14 debug user access disable control bit 0 CP14 debug user access enable this is the reset value 1 CP14 debug user access disable If this bit is set and a User mode process ...

Page 291: ...nchronous Data Aborts generated by instructions issued to the processor through the DBGITR This bit is set to 1 when a synchronous Data Abort occurs while the processor is in debug state and is cleared by writing to the DBGDRCR 2 5 2 MOE Method of entry bits b0000 a DBGDRCR 0 halting debug event occurred b0001 a breakpoint occurred b0100 an EDBGRQ halting debug event occurred b0011 a BKPT instruct...

Page 292: ... to DBGITR InstrCompl and InstrCompl_l are cleared to b0 Debuggers accessing these registers must first read DBGDSCR This has the side effect of copying DTRRXfull and DTRTXfull to DTRRXfull_l and DTRTXfull_l The debugger must then write to the DBGDTRRX if the DTRRXfull flag was b0 DTRRXfull_l is b0 read from the DBGDTRTX if the DTRTXfull flag was b1 DTRTXfull_l is b1 write to the DBGITR if the Ins...

Page 293: ...the instruction that triggers the watchpoint Usage constraints There are no usage constraints Configurations Available in all processor configurations Attributes See Table 12 12 on page 12 20 Figure 12 6 shows the DBGWFAR bit assignments Figure 12 6 DBGWFAR Register bit assignments Table 12 11 Data Transfer Register functions Bits Name Function 31 0 Data Reads the Data Transfer Register This is re...

Page 294: ...when the processor is in Monitor debug mode then the processor ignores the setting and does not generate a vector catch debug event This prevents the processor entering an unrecoverable state The debugger must program these bits to zero when Monitor debug mode is selected and enabled to ensure forward compatibility Configurations Available in all processor configurations Attributes See Table 12 13...

Page 295: ... Table 12 13 DBGVCR Register bit assignments Bits Name Reset value Normal address High vectors address Function Access 31 8 0 Do not modify on writes On reads the value returns zero RAZ or SBZP 7 FIQ 0 0x0000001C 0xFFFF001C Vector catch enable RW 6 IRQ 0x00000018a 0xFFFF0018a Vector catch enable 5 0 Do not modify on writes On reads the value returns zero RAZ or SBZP 4 Data Abort 0 0x00000010 0xFFF...

Page 296: ... 11 Debug Run Control Register The DBGDRCR Register characteristics are Purpose Requests the processor to enter or leave debug state Clears the sticky exception bits present in the DBGDSCR Usage constraints The DBGDRCR is a write only register Configurations Available in all processor configurations Attributes See Table 12 15 on page 12 23 Figure 12 9 on page 12 23 shows the DBGDRCR bit assignment...

Page 297: ...An abandoned transaction does not cause any exception Additional instruction fetches or data accesses after the processor entered debug state have an Unpredictable behavior This bit enables the debugger to progress on a deadlock so the processor can enter debug state For a debug state entry to occur a halting debug event must be requested before this bit is set If you write a 1 to this bit when DB...

Page 298: ...odify on writes and Read As Zero because these registers do not support context ID comparisons The contents of the CP15 Context ID Register give the context ID value for a DBGBVR to match For information on the CONTEXTIDR see Chapter 4 System Control 12 4 13 Breakpoint Control Registers The DBGBCR Register characteristics are Purpose Contains the necessary control bits for setting breakpoints link...

Page 299: ...n address b11111 0x7FFFFFFF mask for instruction address 23 22 20 M Meaning of DBGBVR b000 instruction address match b001 linked instruction address match b010 unlinked context ID b011 linked context ID b100 instruction address mismatch b101 linked instruction address mismatch b11x Reserved For more information see Table 12 18 on page 12 27 19 16 Linked BRP number The binary number encoded here in...

Page 300: ...eakpoint is the negative image of the corresponding instruction address breakpoint If the BRP is programmed for context ID comparison this field must be set to b1111 Otherwise breakpoint and watchpoint debug events might not be generated as expected 4 3 2 1 S Supervisor access control The breakpoint can be conditioned on the mode of the processor b00 User System or Supervisor b01 Privileged b10 Us...

Page 301: ...struction address context ID and state match b010 The corresponding DBGBVR 31 0 is compared against CP15 Context ID Register c13 and the state of the processor against this DBGBCR This BRP is not linked with any other one It generates a breakpoint debug event on a joint context ID and state match For this BRP DBGBCR 8 5 must be set to b1111 Otherwise it is Unpredictable whether a breakpoint debug ...

Page 302: ...usage constraints Configurations Available in all processor configurations Attributes See Table 12 20 on page 12 29 Figure 12 11 shows the DBGWCR bit assignments Figure 12 11 DBGWCR Register bit assignments Table 12 19 Watchpoint Value Register bit assignments Bits Description 31 2 Watchpoint address 1 0 Reserved Do not modify on writes On reads the value returns zero Reserved Linked BRP Byte addr...

Page 303: ...ot being included in the comparison Should Be Zero Otherwise the behavior is Unpredictable To watch for a write to any byte in an 8 byte aligned object of size 8 bytes ARM recommends that a debugger sets DBGWCR 28 24 to b00111 and DBGWCR 12 5 to b11111111 This is compatible with both ARMv7 debug compliant implementations that have an 8 bit DBGWCR 12 5 and with those that have a 4 bit DBGWCR 8 5 by...

Page 304: ...essed bxx1xxxxx The watchpoint hits if the byte at address DBGDSWVR 31 0 0xFFFFFFF8 5 is accessed bx1xxxxxx The watchpoint hits if the byte at address DBGDSWVR 31 0 0xFFFFFFF8 6 is accessed b1xxxxxxx The watchpoint hits if the byte at address DBGDSWVR 31 0 0xFFFFFFF8 7 is accessed 4 3 L S Load store access The watchpoint can be conditioned to the type of access b00 Reserved b01 load load exclusive...

Page 305: ...Figure 12 13 DBGAUTHSTATUS Register bit assignments Table 12 22 shows the DBGAUTHSTATUS bit assignments 31 0 Reserved 1 Lock implemented bit Table 12 21 DBGOSLSR Register bit assignments Bits Name Function 31 1 RAZ 0 Lock implemented bit Indicates that the OS lock functionality is not implemented This bit always reads 0 31 0 3 Reserved 4 5 6 7 8 Secure non invasive debug features implemented Secur...

Page 306: ...ignments Figure 12 14 DBGPRCR Register bit assignments Table 12 23 shows the DBGPRCR bit assignments 5 Secure invasive debug features implemented 0b1 Implemented 4 Secure invasive debug features enabled DBGEN Invasive debug enable field 3 0 Non secure debug featuresa 0x0 Not implemented a Cortex R4 does not implement the Security Extensions so all the debug features are considered secure Table 12 ...

Page 307: ...ssor This bit does not have any effect on initial system power up as nSYSPORESET clears it 0 Do not hold internal reset on power up or warm reset This is the reset value 1 Hold the processor non debug logic in reset on warm reset until this flag is cleared 1 Force internal reset When a 1 is written to this bit the processor asserts the DBGRSTREQ output for four cycles You can connect this output t...

Page 308: ... status bit This bit is cleared on a read 0 the processor has not been reset since the last time this register was read 1 the processor has been reset since the last time this register was read This is the reset value This sticky bit is set to 1 when nSYSPORESET is asserted 2 Reset status Reset status bit 0 the processor is not held in reset 1 the processor is held in reset 1 Sticky power down sta...

Page 309: ...ssor Identification Registers See Processor ID Registers 0xF00 960 RW ITCTRL Integration Mode Control Registers See Integration Mode Control Register on page 13 8 0xFA0 1000 CLAIMSET Claim Tag Set Register See Claim Tag Set Register on page 12 36 0xFA4 1001 CLAIMCLR Claim Tag Clear Register See Claim Tag Clear Register on page 12 37 0xFB0 1004 W LOCKACCESS Lock Access Register See Lock Access Regi...

Page 310: ... assignments 0xD10 836 MPUIR MPU Type Register 0xD14 837 MPIDR Multiprocessor Affinity Register 0xD18 0xD1C 838 839 Alias of MIDR 0xD20 840 ID_PFR0 Processor Feature Register 0 0xD24 841 ID_PFR1 Processor Feature Register 1 0xD28 842 ID_DFR0 Debug Feature Register 0 0xD2C 843 ID_AFR0 Auxiliary Feature Register 0 0xD30 844 ID_MMFR0 Processor Feature Register 0 0xD34 845 ID_MMFR1 Memory Model Featur...

Page 311: ... returns the current claim tag value writing 0 to a CLAIM bit has no effect writing 1 to a specific claim tag clear bit clears that claim tag Configurations Available in all processor configurations Attributes See Table 12 28 Figure 12 17 shows the DBGCLAIMCLR bit assignments Figure 12 17 DBGCLAIMCLR Register bit assignments Table 12 28 shows the DBGCLAIMCLR bit assignments Writing b1 to a specifi...

Page 312: ...se Returns the current lock status of the debug registers Usage constraints The DBGLSR is a read only register only defined in the memory mapped interface Configurations Available in all processor configurations Attributes See Table 12 29 Figure 12 18 shows the DBGLSR bit assignments Figure 12 18 DBGLSR Register bit assignments Table 12 29 shows the DBGLSR bit assignments 12 5 5 Device Type Regist...

Page 313: ...gisters identify the processor as a CoreSight component Only bits 7 0 of each register are used the remaining bits Read As Zero The values in these registers are fixed Table 12 31 shows the offset value register number and description that are associated with each Peripheral Identification Register 31 31 0 Reserved 4 Sub type Main class 8 7 3 Table 12 30 DBGDEVTYPE Register bit assignments Bits Na...

Page 314: ...r the processor is 0xC14 Revision 4 bits Indicates the major and minor revision of the product The major revision contains functionality changes and the minor revision contains bug fixes for the product The revision number starts at 0x0 and increments by 1 at both major and minor revisions RevAnd 4 bits Indicates the manufacturer revision number This number starts at 0x0 and increments by the inte...

Page 315: ...anufacturer revision number This value changes based on the metal fixes made by the manufacturer 3 0 0x0 Customer modified See Table 12 32 on page 12 40 Table 12 37 Peripheral ID Register 4 functions Bits Value Description 31 8 Reserved 7 4 0x0 Indicates the number of blocks the debug component occupies This field is always set to 0 3 0 0x4 Indicates the JEDEC JEP106 continuation code For the proc...

Page 316: ...s are only generated if the instruction passes its condition code A breakpoint debug event This occurs when An instruction was fetched and the instruction address or the CP15 Context ID register c13 matched the breakpoint value At the same time the instruction was fetched all the conditions of the DBGBCR for unlinked context ID breakpoint generation matched the instruction side control signals The...

Page 317: ...led the BKPT instruction generates a debug exception Prefetch Abort All other software debug events are ignored When DBGEN is LOW debug is disabled regardless of the value of DBGDSCR 15 14 Table 12 39 shows the behavior of the processor on debug events 12 6 4 Debug event priority Breakpoint instruction address or CID match vector catch and halting debug events have the same priority If more than o...

Page 318: ...or Note The Prefetch Abort handler is responsible for checking the IFSR to determine if a debug exception or other kind of Prefetch Abort exception caused the exception entry If the cause is a debug exception the Prefetch Abort handler must branch to the debug monitor The R14_abt register holds the address of the instruction to restart If the processor takes a debug exception because of a watchpoi...

Page 319: ... offset 8 for ARM state 4 for Thumb state If the processor takes a debug exception because of a breakpoint BKPT or vector catch debug event the processor performs the following actions on these registers it updates the IFSR with the debug event encoding it writes an Unpredictable value to the IFAR it does not change the DFSR DFAR or DBGWFAR 12 7 2 Avoiding unrecoverable states The processor ignore...

Page 320: ...t only request the debugger to write b00 to DBGBCR 2 1 if you know that the abort handler does not switch to one of the USR SYS or SVC mode before saving the context that might be corrupted by a later debug event You must also be careful about requesting the debugger to set a breakpoint or BKPT debug event inside a Prefetch Abort or Data Abort handler or a watchpoint debug event on a data address ...

Page 321: ... on non invasive debug on page 12 50 Effects of debug events on processor registers on page 12 50 Exceptions in debug state on page 12 50 Leaving debug state on page 12 51 12 8 1 Entering debug state When a debug event occurs while the processor is in Halting debug mode it switches to a special state called debug state so the debugger can take control You can configure Halting debug mode by settin...

Page 322: ...ent reads from the PC return an Unpredictable value If the debugger forces the processor to execute an instruction that writes to the PC and this instruction fails its condition codes the PC is written with an Unpredictable value That is if the debugger forces the processor to restart the restart address is Unpredictable Also if the debugger reads the PC the read value is Unpredictable While the p...

Page 323: ...normal state When not in debug state an MSR instruction that modifies the execution state bits in the CPSR is Unpredictable However in debug state an MSR instruction can update the execution state bits in the CPSR An Instruction Synchronization Barrier ISB sequence must follow a direct modification of the execution state bits in the CPSR by an MSR instruction When not in debug state an MRS instruc...

Page 324: ...4_abt registers In addition the processor does not update any coprocessor registers including the CP15 IFSR DFSR DFAR or IFAR registers except for CP14 DBGDSCR 5 2 method of entry bits These bits indicate the type of debug event that caused the entry into debug state Note On entry to debug state the processor updates the DBGWFAR register with the address of the instruction accessing the watchpoint...

Page 325: ...hat any outstanding asynchronous Data Aborts are detected before starting debug operations If the DSB operation detects an asynchronous Data Abort the processor records this event and its type as if the CPSR A bit was set The purpose of latching this event is to ensure that it can be taken on exit from the debug state Before forcing the processor to leave debug state the debugger must execute a DS...

Page 327: ... DBGDSCCR is set to 0 while the processor is in debug state then the processor treats any memory access that hits in L1 data cache as write through regardless of the memory region attributes This guarantees that the L1 instruction cache can see the changes to the code region without the debugger executing a time consuming and device specific sequence of cache clean operations After the code is wri...

Page 328: ...cessor to enter debug state When this occurs the DBGDSCR 5 2 method of debug entry bits are set to b0100 When EDBGRQ is asserted it must be held until DBGACK is asserted Failure to do so leads to Unpredictable behavior of the processor DBGACK The processor asserts DBGACK to indicate that the system has entered debug state It serves as a handshake for the EDBGRQ signal The DBGACK signal is also dri...

Page 329: ... it is ready to exit debug halt state and return to normal run state DBGTRIGGER The processor asserts DBGTRIGGER to indicate that the system has accepted a debug request and attempts to enter debug state It is not a handshake for the EDBGRQ signal If DBGACK does not go HIGH following DBGTRIGGER the memory system has stopped responding and the processor has not entered debug state Table A 13 on pag...

Page 330: ...ier DSB instruction 3 Poll the DBGDSCR or Authentication Status Register to check whether the processor has already detected the changed value of these signals This is required because the system might not issue the signal change to the processor until several cycles after the DSB completes 4 Issue an Instruction Synchronization Barrier ISB instruction The software cannot perform debug or analysis...

Page 331: ...dress reg_num 2 WriteDebugRegister int reg_num uint32 val write the value val to the debug register reg_num at address reg_num 2 A basic function for using the debug state is executing an instruction through the DBGITR Example 12 1 shows the sequence for executing an ARM instruction through the DBGITR Example 12 1 Executing an ARM instruction through the DBGITR ExecuteARMInstruction uint32 instr S...

Page 332: ... the CP14 DBGDSCR returns 0 for the DTRTXfull flag a following read of the CP14 DTR returns an Unpredictable value a following write to the CP14 DTR writes the intended 32 bit word and sets DTRRXfull to 1 No prefetch flush is required between these two CP14 instructions When Nonblocking mode is selected for DTR accesses the following conditions are true for memory mapped DBGDSCR memory mapped DBGD...

Page 333: ...he host to target channel Example 12 3 Host to target data transfer target end r0 word sent by the debugger ReadDCC MRC p14 0 PC c0 c1 0 BCC ReadDCC MRC p14 0 Rd c0 c5 0 BX lr Debugger access to the DCC When not in debug state a debugger can access the DCC through the external interface The following examples show the pseudo code operations for these accesses Example 12 4 shows the code for target...

Page 334: ...er 34 if dscr 1 29 DBGDTRTX target host transfer register full dtr ReadDebugRegister 35 ProcessTargetToHostWord dtr if dscr 1 30 DBGDTRRX host target transfer register empty dtr GetNextHostToTargetWord WriteDebugRegister 32 dtr 12 11 2 Programming breakpoints and watchpoints This section describes the following operations Programming simple breakpoints and the byte address select Setting a simple ...

Page 335: ...hen JAZELLE byte_address_select 1 address 3 when THUMB byte_address_select 3 address 2 when ARM byte_address_select 15 Step 4 Write the mask and control register to enable the breakpoint breakpoint WriteDebugRegister 80 break_num 7 byte_address_select 5 Setting a simple aligned watchpoint The simplest and most common type of watchpoint watches for a write to a given address in memory In practice a...

Page 336: ...hen 2 byte_address_select 3 address 6 when 4 byte_address_select 15 address 4 when 8 byte_address_select 255 Step 4 Write the mask and control register to enable the watchpoint breakpoint WriteDebugRegister 112 watch_num 23 byte_address_select 5 Setting a simple unaligned watchpoint Using the byte address select bits certain unaligned objects up to a doubleword 64 bits can be watched in a single w...

Page 337: ...ster 112 watch_num 1 23 byte_address_select 0xFF00 3 Step 6 Return flag to caller indicating if second watchpoint was used return byte_address_select 256 12 11 3 Single stepping You can use the breakpoint mismatch bit to implement single stepping on the processor Unlike high level stepping single stepping implements a low level step that executes a single instruction at a time With high level step...

Page 338: ...recursive function might terminate with BL ThisFunction POP saved_registers pc In this case the POP instruction loads a link register that is saved at the start of the function and if that is the link register created by the BL instruction shown it points back at the POP instruction Therefore this single step code unwinds the entire call stack to the point of the original caller rather than steppi...

Page 339: ...hod_of_debug_entry state dscr 2 0xF if method_of_debug_entry 2 method_of_debug_entry 10 state dbgwfar ReadDebugRegister 6 12 11 5 Debug state exit When exiting debug state the program counter must always be written If the execution state or CPSR must be changed this must be done before writing to the PC because writing to the CPSR can affect the PC Having restored the program state the debugger ca...

Page 340: ...2 68 Fast register read write on page 12 70 Fast memory read write on page 12 71 Accessing coprocessor registers on page 12 72 Reading and writing registers through the DCC To read a single register the debugger can use the sequence that Example 12 13 shows This sequence depends on two other sequences Executing an ARM instruction through the DBGITR on page 12 57 and Target to host data transfer ho...

Page 341: ...ow contains the PC pc ReadRegister 0 Step 4 Restore the value of R0 WriteRegister 0 saved_r0 return pc Note You can use a similar sequence to write to the PC to set the return address when leaving debug state Reading the CPSR in debug state Example 12 16 shows the code for reading the CPSR Example 12 16 Reading the CPSR ReadCPSR Step 1 Save R0 saved_r0 ReadRegister 0 Step 2 Execute instruction MRS...

Page 342: ...mple 12 18 Reading a byte of memory uint8 ReadByte uint32 address bool aborted Step 1 Save the values of R0 and R1 saved_r0 ReadRegister 0 saved_r1 ReadRegister 1 Step 2 Write the address to R0 WriteRegister 0 address Step 3 Execute the instruction LDRB R1 R0 through the DBGITR ExecuteARMInstruction 0xE5D01000 Step 4 Read the value of R1 that contains the data at the address datum ReadRegister 1 S...

Page 343: ...ress bool aborted uint8 data int nbytes Step 1 Save the value of R0 and R1 saved_r0 ReadRegister 0 saved_r1 ReadRegister 1 Step 2 Write the address to R0 WriteRegister 0 address while nbytes 0 Step 3 Execute instruction LDRB R1 R0 1 through the DBGITR ExecuteARMInstruction 0xE4D01001 Step 4 Read the value of R1 that contains the data at the address data ReadRegister 1 nbytes Step 5 Restore the cor...

Page 344: ...ing the DCC into stall mode and by writing the value 1 to the DCC access mode bits For more information see CP14 c1 Debug Status and Control Register on page 12 14 Example 12 22 shows the sequence to change the DTR access mode Example 12 22 Changing the DTR access mode SetDTRAccessMode int mode Step 1 Write the mode value to DBGDSCR 21 20 dscr ReadDebugRegister 34 dscr dscr 0x3 20 mode 20 WriteDeb...

Page 345: ...ing use of the DTR access mode Example 12 25 shows the sequence for reading a block of words of memory Example 12 25 Reading a block of words of memory ReadWords uint32 address bool aborted uint32 data int nwords Step 1 Write the value 0b01 to DBGDSCR 21 20 for stall mode SetDTRAccessMode 1 Step 2 Save the value of R0 saved_r0 ReadRegisterInStallMode 0 Step 3 Write the address to read from to the ...

Page 346: ...tep 5 Write the opcode for STC p14 c5 R0 4 to the DBGITR Write stalls until the DBGITR is ready but the instruction is not issued WriteDebugRegister 33 0xECA05E01 Step 6 Loop writing the data Each time a word is written to the DBGDTRRX the instruction is reissued while nwords 0 WriteDebugRegister 35 data nwords Step 7 Write the value b00 to DBGDSCR 21 20 for normal mode SetDTRAccessMode 0 Step 8 R...

Page 347: ...nt CPnum int opc1 int CRn int CRm int opc2 Step 1 Save R0 saved_r0 ReadRegister 0 Step 2 Execute instruction MCR p15 0 R0 c0 c1 0 through the DBGITR ExecuteARMInstruction 0xEE000010 CPnum 8 opc1 21 CRn 16 CRm opc2 5 Step 3 Read the value of R0 that now contains the CP register CP15c1 ReadRegister 0 Step 4 Restore the value of R0 WriteRegister 0 saved_r0 return CP15c1 ...

Page 348: ...es up from standby the APB access is held by keeping the PREADYDBG signal LOW 12 12 1 Emulating power down By writing to bit 0 of the DBGPRCR the debugger asserts the DBGNOPWRDWN output The expected usage model of this signal is that it connects to the system power controller and that when HIGH it indicates that this controller must work in emulate mode On a power down request from the processor i...

Page 349: ...tial Attaching the debugger for a postmortem debug session is not possible because setting the DBGNOPWRDWN signal to 1 might not cause the processor to power up The effect of setting DBGNOPWRDWN to 1 when the processor is already powered down is implementation defined and is up to the system designer ...

Page 350: ...Integration Test Registers This chapter describes how to use the Integration Test Registers in the processor It contains the following sections About Integration Test Registers on page 13 2 Summary of the processor registers used for integration testing on page 13 3 Processor integration testing on page 13 4 ...

Page 351: ...of the design and enable topology detection of the design using debug tools The Integration Mode Control Register DBGITCTRL that is also described in this chapter controls the use of the Integration Test Registers When programming the Integration Test Registers you must enable all the changes at the same time For more information about the Integration Test Registers and the Integration Mode Contro...

Page 352: ...est Registers summary Register name Base offset Default value Type Clock domain Description Integration Test Registers DBGITETMIF 0xED8 a WO CLK See DBGITETMIF Register ETM interface on page 13 6 DBGITMISCOUT 0xEF8 n a WO CLK See DBGITMISCOUT Register Miscellaneous Outputs on page 13 7 DBGITMISCIN 0xEFC a RO CLK See DBGITMISCIN Register Miscellaneous Inputs on page 13 7 Integration Mode Control Re...

Page 353: ... the read only Integration Test Registers to read the state of some of the processor inputs Table 13 3 on page 13 5 shows the signals that you can read in this way There are Integration Test Registers that you can use in conjunction with ETM R4 integration For more information see the ETM R4 Technical Reference Manual Table 13 2 Output signals that can be controlled by the Integration Test Registe...

Page 354: ... 2 Performing integration testing When you perform integration testing or topology detection You must ensure that the other ETM interface signals cannot change value during integration testing ARM strongly recommends that the processor is halted while in debug state because toggling input and output pins might have an unwanted effect on the operation of the processor You must not set the DBGITCTRL...

Page 355: ...TMIF Register bit assignments Bits Name Function 31 15 Reserved Write as zero 14 EVNTBUS 46 Set value of the EVNTBUS 46 output pina a Not available on r0px revisions of the processor 13 EVNTBUS 28 Set value of the EVNTBUS 28 output pin 12 EVNTBUS 0 Set value of the EVNTBUS 0 output pin 11 ETMCID 31 Set value of the ETMCID 31 output pin 10 ETMCID 0 Set value of the ETMCID 0 output pin 9 ETMDD 63 Se...

Page 356: ...nputs The DBGITMISCIN Register at offset OxEFC is read only Figure 13 3 on page 13 8 shows the register bit assignments Reserved 31 5 4 3 0 nPMUIRQ DBGTRIGGER 6 2 1 COMMTX Reserved DBGACK COMMRX 7 8 9 10 Reserved DBGRESTARTED ETMWFIPENDING Table 13 5 DBGITMISCOUT Register bit assignments Bits Name Function 31 10 Reserved Write as zero 9 DBGRESTARTED Set value of the DBGRESTARTED output pin 8 DBGTR...

Page 357: ...served nETMWFIREADY Reserved nFIQ nIRQ EDBGRQ Reserved DBGRESTART 11 12 1 Table 13 6 DBGITMISCIN Register bit assignments Bits Name Function 31 12 Reserved Read Undefined 11 DBGRESTART Read value of the DBGRESTART input pin 10 Reserved Read Undefined 9 8 ETMEXTOUT Read value of the ETMEXTOUT 1 0 input pins 7 6 Reserved Read Undefined 5 nETMWFIREADY Reads the nETMWFIREADY input pin Although this pi...

Page 358: ... mode or in integration mode where the inputs and outputs of the device can be directly controlled for the purpose of integration testing or topology detection For more information see the ARM Architecture Reference Manual Table 13 7 DBGITCTRL Register bit assignments Bits Access Reset value Name Function 31 1 RAZ SBZP Reserved 0 R W 0 INTMODE Controls whether the processor is in normal operating ...

Page 359: ...escriptions on page A 2 Global signals on page A 3 Configuration signals on page A 4 Interrupt signals including VIC interface signals on page A 7 L2 interface signals on page A 8 TCM interface signals on page A 13 Redundant processor signals on page A 16 Debug interface signals on page A 17 ETM interface signals on page A 19 Test signals on page A 20 MBIST signals on page A 21 Validation signals ...

Page 360: ...clocking column that indicates by which clock a signal is sampled or driven All signals are sampled on or driven from the rising edge of the clock The clocking column can also contain the following information Any Means the input is synchronised inside the processor so the input can be driven from any clock Tie off Means the input must be tied to a fixed value Reset Means the input must only be ch...

Page 361: ...re clock CLKIN Input Core clock CLKIN2 Input Core clock in phase with DUALCKLIN for configurations with dual redundant core a nRESET Input Any Core reset nSYSPORESET Input Any System power on reset nCPUHALT Input Any Processor halt after reset DBGNOCLKSTOP Input Any Processor does not stop the clocks when entering WFI state a DUALCLKIN Input Clock for second redundant core a DUALCLKIN2 Input Clock...

Page 362: ...INITRAMA Input Tie off Reset Reset value of ATCM enable bit When HIGH indicates Tightly Coupled Memory A ATCM enabled at reset See c9 ATCM Region Register on page 4 62 for more information INITRAMB Input Tie off Reset Reset value of BTCM bit When HIGH indicates Tightly Coupled Memory B BTCM enabled at reset See c9 BTCM Region Register on page 4 61 for more information LOCZRAMA Input Tie off Reset ...

Page 363: ...trol Register on page 4 37 for more information ENTCM1IF Input Tie off Enable B1TCM interface Use B0TCM only if this signal not tied HIGH PARECCENRAM 2 0 Input Tie off Reset TCMs parity or ECC check enable Tie each bit HIGH to enable parity or ECC checking on the appropriate TCM at reset Use following values 2 B1TCMa 1 B0TCMa 0 ATCM See c1 Auxiliary Control Register on page 4 40 for more informati...

Page 364: ... enable bits reset values Tie each bit high to enable read modify write for TCM interfaces at reset c Use the following values 1 BTCM 0 ATCM See c1 Auxiliary Control Register on page 4 40 for more information SLBTCMSB Input Tie off Use most significant bit of BTCM address to select B1TCM if this signal is HIGH Use bit 3 of the BTCM address if this signal is LOW a If the BTCM is configured with ECC...

Page 365: ... inputs are synchronous to CLKIN IRQADDRV Input CLKINd Anye Indicates IRQADDR is valid IRQADDRVSYNCEN Input Tie off Tie HIGH if the IRQADDRV input from the VIC is asynchronous to CLKIN Tie HIGH if the IRQADDRV input from the VIC is synchronous to CLKIN IRQADDR 31 2 Input Address of the IRQ This signal must be stable when IRQADDRV is asserted IRQACK Output CLKIN Acknowledges interrupt nPMUIRQ Outpu...

Page 366: ...N Clock enable for the AXI master port Write address channel AWADDRM 31 0 Output CLKIN Transfer start address AWBURSTM 1 0 Output CLKIN Write burst type AWCACHEM 3 0 Output CLKIN Provides decode information for outer attributes b0000 Strongly ordered b0001 Device b0011 Normal Non cacheable b0110 Normal cacheable write through b1111 Normal cacheable write back write allocation b0111 Normal cacheabl...

Page 367: ...cates that the core is ready to accept write response BRESPM 1 0 Input CLKIN Write response BVALIDM Input CLKIN Indicates that a valid write response is available Read address channel ARADDRM 31 0 Output CLKIN Instruction fetch burst start address ARBURSTM 1 0 Output CLKIN Burst type ARCACHEM 3 0 Output CLKIN Provides decode information for outer attributes b0000 Strongly ordered b0001 Device b001...

Page 368: ...l RDATAM 63 0 Input CLKIN Read data RIDM 3 0 Input CLKIN The identification tag for the read data group of signals RLASTM Input CLKIN Indicates the last transfer in a read burst RREADYM Output CLKIN Read ready signal indicating that the bus master can accept read data and response information RRESPM 1 0 Input CLKIN Read response RVALIDM Input CLKIN Indicates that read data is available Table A 4 A...

Page 369: ...Output CLKIN Address ready The slave uses this signal to indicate that it can accept the address AWSIZES 2 0 Input CLKIN Indicates the size of the transfer AWUSERS 3 0 Input CLKIN Memory type select data cache instruction cache BTCM or ATCM one hot AWUSERS 3 0 signal is not part of the standard AXI specification AWVALIDS Input CLKIN Indicates address and control are valid Write Data Channel WDATAS...

Page 370: ...ut CLKIN Indicates address and control are valid Read Data Channel RDATAS 63 0 Output CLKIN Read data RIDS 7 0 Output CLKIN The identification tag for the read data group of signals RLASTS Output CLKIN Indicates the last transfer in a read burst RREADYS Input CLKIN Read ready signal indicating that the bus master can accept read data and response information RRESPS 1 0 Output CLKIN Read response R...

Page 371: ...CM data RAM ATCBYTEWR 7 0 Output CLKIN Byte strobes for direct write ATCSEQ Output CLKIN ATCM RAM access is sequential ATCDATAOUT 63 0 Output CLKIN Write data for ATCM data RAM ATCPARITYOUT 13 0 Output CLKIN Write parity or ECC code for ATCM ATCACCTYPE 2 0 Output CLKIN Determines access type b001 Load Store b010 Fetch b100 DMA b100 MBISTc a This signal is ignored when bit 0 of the Auxiliary Contro...

Page 372: ...al is ignored when bit 1 of the Auxiliary Control Register is set to 0 see c1 Auxiliary Control Register on page 4 40 b Only generated if the processor is configured to include TCM address bus parity c The MBIST interface has no way of signaling a wait If it is accessing the TCM and the TCM signals a wait the AXI slave pipeline stalls and the data arrives later However no signal is sent to the MBI...

Page 373: ...ACCTYPE 2 0 Output CLKIN Determines access type b001 Load Store b010 Fetch b100 DMA b100 MBISTc a This signal is ignored when bit 2 of the Auxiliary Control Register is set to 0 see c1 Auxiliary Control Register on page 4 40 b Only generated if the processor is configured to include TCM address bus parity c The MBIST interface has no way of signaling a wait If it is accessing the TCM and the TCM s...

Page 374: ...A 11 Dual core interface signals Signal Direction Clocking Description DCCMINP 7 0 Input a a Implementation defined Dual core compare logic input control bus DCCMOUT 7 0 Output a Dual core compare logic output control bus DCCMINP2 7 0 Input a Dual core compare logic extra input control busb b Not available in r0px revisions of the processor DCCMOUT2 7 0 Output a Dual core compare logic extra outpu...

Page 375: ...s PENABLEDBG Input PCLKDBG Indicates second and subsequent cycle of a transfer PREADYDBG Output PCLKDBG Extends a APB transfer by the inserting wait states PSLVERRDBG Output PCLKDBG Slave generated error response PWRITEDBG Input PCLKDBG Indicates access is a write transfer Distinguishes between a read LOW and a write HIGH PRESETDBGn Input Any Reset debug logic Table A 13 Debug miscellaneous signal...

Page 376: ...al DBGROMADDRV Input Tie off Debug ROM physical address valid DBGSELFADDR 31 12 Input Tie off Debug self address offset DBGSELFADDRV Input Tie off Debug self address offset valid a Not available in r0px revisions of the processor Table A 13 Debug miscellaneous signals continued Name Direction Clocking Description ...

Page 377: ...ETMIA 31 1 Output CLKIN ETM instruction address ETMDCTL 11 0 Output CLKIN ETM data control bus ETMDA 31 0 Output CLKIN ETM data address ETMDD 63 0 Output CLKIN ETM data data ETMCID 31 0 Output CLKIN Value of processor CID register ETMWFIPENDING Output CLKIN Core is attempting to enter WFI state EVNTBUS 46 0 Output CLKIN Performance monitor unit output ETMPWRUP Input CLKIN Power up ETM interface nE...

Page 378: ...Limited All rights reserved A 20 ID073015 Non Confidential A 10 Test signals Table A 15 shows the test signals Table A 15 Test signals Signal Direction Clocking Description SE Input a a Design for test only Scan Enable RSTBYPASS Input a Bypass pipelined reset ...

Page 379: ... signals Table A 16 MBIST signals Signal Direction Clocking Description MBTESTON Input CLKIN MBIST test is enabled MBISTDIN 77 0 Input CLKIN MBIST data in MBISTADDR 19 0 Input CLKIN MBIST address MBISTCE Input CLKIN MBIST chip enable MBISTSEL 4 0 Input CLKIN MBIST chip select MBISTWE 7 0 Input CLKIN MBIST write enable MBISTDOUT 77 0 Output CLKIN MBIST data out ...

Page 380: ...tial A 12 Validation signals Table A 17 shows the validation signals Table A 17 Validation signals Signal Direction Clocking Description VALEDBGRQ Output CLKIN Debug request nVALIRQ Output CLKIN Request for an interrupt nVALFIQ Output CLKIN Request for a Fast Interrupt nVALRESET Output CLKIN Request for a reset ...

Page 381: ...point logic Table A 18 FPU signals Signal Direction Clocking Description FPIXC Output CLKIN Masked floating point inexact exception FPOFC Output CLKIN Masked floating point overflow exception FPUFC Output CLKIN Masked floating point underflow exception FPIOC Output CLKIN Masked floating point invalid operation exception FPDZC Output CLKIN Masked floating point divide by zero exception FPIDC Output...

Page 382: ...ed All rights reserved B 1 ID073015 Non Confidential Appendix B AC Characteristics This chapter gives the timing parameters for the processor It contains the following sections Processor timing on page B 2 Processor timing parameters on page B 3 ...

Page 383: ...onforms to the AMBA AXI Specification For the relevant timing of the AXI write and read transfers and the error response see the AMBA AXI Protocol Specification The APB debug interface of the processor conforms to the AMBA 3 APB Protocol Specification For the relevant timing of the APB write and read transfers and the error response see the AMBA 3 APB Protocol Specification ...

Page 384: ... B 1 shows the timing parameters for the miscellaneous input ports Table B 2 shows the timing parameters for the configuration input port Table B 1 Miscellaneous input ports timing parameters Input delay minimum Input delay maximum Signal name Clock uncertainty 10 nRESET Clock uncertainty 10 nSYSPORESET Clock uncertainty 10 PRESETDBGn Clock uncertainty 50 nCPUHALT Clock uncertainty 20 DBGNOCLKSTOP...

Page 385: ...lock uncertainty 60 nIRQ Clock uncertainty 10 INTSYNCEN Clock uncertainty 60 IRQADDRV Clock uncertainty 60 IRQADDRVSYNCEN Clock uncertainty 60 IRQADDR 31 2 Table B 4 AXI master input port timing parameters Input delay minimum Input delay maximum Signal name Clock uncertainty 50 ACLKENM Clock uncertainty 60 AWREADYM Clock uncertainty 60 WREADYM Clock uncertainty 60 BIDM 3 0 Clock uncertainty 60 BRE...

Page 386: ...k uncertainty 60 AWSIZES 2 0 Clock uncertainty 60 AWBURSTS 1 0 Clock uncertainty 60 AWPROTS Clock uncertainty 60 AWUSERS 3 0 Clock uncertainty 60 AWVALIDS Clock uncertainty 60 WDATAS 63 0 Clock uncertainty 60 WSTRBS 7 0 Clock uncertainty 60 WLASTS Clock uncertainty 60 WVALIDS Clock uncertainty 60 BREADYS Clock uncertainty 60 ARIDS 7 0 Clock uncertainty 60 ARADDRS 22 0 Clock uncertainty 60 ARLENS 3...

Page 387: ...50 EDBGRQ Clock uncertainty 50 PCLKENDBG Clock uncertainty 50 PSELDBG Clock uncertainty 50 PADDRDBG 11 2 Clock uncertainty 50 PADDRDBG31 Clock uncertainty 50 PWDATADBG 31 0 Clock uncertainty 50 PENABLEDBG Clock uncertainty 50 PWRITEDBG Clock uncertainty 10 DBGROMADDR 31 12 Clock uncertainty 10 DBGROMADDRV Clock uncertainty 10 DBGSELFADDR 31 12 Clock uncertainty 10 DBGSELFADDRV Clock uncertainty 50...

Page 388: ...ock uncertainty 50 MBISTCE Clock uncertainty 50 MBISTSEL 4 0 Clock uncertainty 50 MBISTWE 7 0 Table B 9 TCM interface input ports timing parameters Input delay minimum Input delay maximum Signal name Clock uncertainty 65 ATCDATAIN 63 0 Clock uncertainty 65 ATCPARITYIN 13 0 Clock uncertainty 65 ATCERROR Clock uncertainty 50 ATCWAIT Clock uncertainty 40 ATCLATEERROR Clock uncertainty 50 ATCRETRY Clo...

Page 389: ...output port Clock uncertainty 50 B1TCWAIT Clock uncertainty 40 B1TCLATEERROR Clock uncertainty 50 B1TCRETRY Table B 9 TCM interface input ports timing parameters continued Input delay minimum Input delay maximum Signal name Table B 10 Miscellaneous output port timing parameter Output delay minimum Output delay maximum Signal name Clock uncertainty 10 STANDBYWFI Table B 11 Interrupt output ports ti...

Page 390: ...ADDRM 31 0 Clock uncertainty 60 ARLENM 3 0 Clock uncertainty 60 ARSIZEM 2 0 Clock uncertainty 60 ARBURSTM 1 0 Clock uncertainty 60 ARLOCKM 1 0 Clock uncertainty 60 ARCACHEM 3 0 Clock uncertainty 60 ARPROTM 2 0 Clock uncertainty 60 ARUSERM 4 0 Clock uncertainty 60 ARVALIDM Clock uncertainty 60 RREADYM Clock uncertainty 60 AWPARITYM Clock uncertainty 60 WPARITYM Clock uncertainty 60 ARPARITYM Clock ...

Page 391: ...Clock uncertainty 60 BPARITYS Clock uncertainty 60 RPARITYS Clock uncertainty 50 AXISPARERR 2 0 Table B 14 Debug interface output ports timing parameters Output delay minimum Output delay maximum Signal name Clock uncertainty 50 PRDATADBG 31 0 Clock uncertainty 50 PREADYDBG Clock uncertainty 50 PSLVERRDBG Clock uncertainty 50 DBGNOPWRDWN Clock uncertainty 50 DBGACK Clock uncertainty 50 DBGTRIGGER ...

Page 392: ...tainty 50 ETMDD 63 0 Clock uncertainty 50 ETMCID 31 0 Clock uncertainty 50 ETMWFIPENDING Clock uncertainty 50 EVNTBUS 46 0 Table B 16 Test output ports timing parameters Output delay minimum Output delay maximum Signal name Clock uncertainty 50 MBISTDOUT 71 0 Clock uncertainty 50 nVALIRQ Clock uncertainty 50 nVALFIQ Clock uncertainty 50 nVALRESET Clock uncertainty 50 VALEDBGRQ Table B 17 TCM inter...

Page 393: ...y 45 B0TCADDRPTY Clock uncertainty 45 B1TCEN0 Clock uncertainty 45 B1TCEN1 Clock uncertainty 45 B1TCADDR 23 0 Clock uncertainty 45 B1TCBYTEWR 7 0 Clock uncertainty 45 B1TCSEQ Clock uncertainty 45 B1TCDATAOUT 63 0 Clock uncertainty 45 B1TCPARITYOUT 13 0 Clock uncertainty 45 B1TCACCTYPE 2 0 Clock uncertainty 45 B1TCWE Clock uncertainty 45 B1TCADDRPTY Table B 18 FPU output port timing parameters Outp...

Page 394: ...M Limited All rights reserved B 13 ID073015 Non Confidential The timing parameters for the dual redundant core compare logic output buses DCCMOUT 7 0 and DCCMOUT2 7 0 are implementation defined Contact the implementer of the macrocell you are working with ...

Page 395: ...bsolute Differences SAD on page C 11 Multiplies on page C 12 Divide on page C 14 Branches on page C 15 Processor state updating instructions on page C 16 Single load and store instructions on page C 17 Load and Store Double instructions on page C 20 Load and Store Multiple instructions on page C 21 RFE and SRS instructions on page C 24 Synchronization instructions on page C 25 Coprocessor instruct...

Page 396: ...and Interlock Behavior ARM DDI 0363G Copyright 2006 2011 ARM Limited All rights reserved C 2 ID073015 Non Confidential Floating point double precision data processing instructions on page C 33 Dual issue on page C 34 ...

Page 397: ...truction sequences to run without pipeline stalls General forwarding occurs from the end of the Ex2 and Wr pipeline stages In addition the multiplier contains an internal multiply accumulate forwarding path The address generation unit also contains an internal forwarding path Most instructions do not require a register until the Ex2 stage All result latencies are given as the number of cycles unti...

Page 398: ...uctions Most instructions do not take more or fewer cycles to execute if they are flag setting The exceptions to this are certain multiply instructions C 1 4 Definition of terms Table C 1 gives descriptions of cycle timing terms used in this chapter Table C 1 Definition of cycle timing terms Term Description Memory Cycles This is the number of cycles during which an instruction sends a memory acce...

Page 399: ...specified registers are required at the start of the Iss stage Add two cycles to the Result Latency of the instruction producing this register or one cycle if the instruction producing this register is an LDM LDR LDRD LDREX or LDRT The lower Result Latency does not apply if this register is the base register of the load instruction producing this register or if the load instruction is an LDRB LDRB...

Page 400: ...lt latency of one Table C 2 Register interlock examples Instruction sequence Behavior LDR R1 R2 ADD R6 R5 R4 Takes two cycles because there are no register dependencies ADD R1 R2 R3 ADD R9 R6 R1 Takes two cycles because ADD instructions have a result latency of one LDR R1 R2 ADD R6 R5 R1 Takes three cycles because of the result latency of R1 ADD R2 R5 R6 LDR R1 R2 Takes four cycles because of the ...

Page 401: ...if their destination is the PC You can substitute ADD with any data processing instruction except for a CLZ A CLZ with the PC as the destination is an Unpredictable instruction For condition code failing cycle counts the cycles for the non PC destination variants must be used Table C 3 Data Processing Instruction cycle timing behavior if destination is not PC Example instruction Cycles Early Reg L...

Page 402: ...hifter requires are Early Regs and require an additional cycle of result availability before use For example the following sequence introduces a 1 cycle interlock and takes three cycles to execute ADD R1 R2 R3 ADD R4 R5 R1 LSL 1 The second source register that is not shifted does not incur an extra data dependency check Therefore the following sequence takes two cycles to execute ADD R1 R2 R3 ADD ...

Page 403: ...SUB instructions These instructions perform saturating arithmetic They have a result latency of two The QDADD and QDSUB instructions must double and saturate the register Rn before the addition This register is an Early Reg Table C 5 shows the cycle timing behavior for QADD QDADD QSUB and QDSUB instructions Table C 5 QADD QDADD QSUB and QDSUB instruction cycle timing behavior Instructions Cycles E...

Page 404: ...s requiring an Early Reg Table C 6 Media data processing instructions cycle timing behavior Instructions Cycles Early Reg Result latency SADD16 SSUB16 SADD8 SSUB8 1 1 UADD16 USUB16 UADD8 USUB8 1 1 SEL 1 1 QADD16 QSUB16 QADD8 QSUB8 1 2 SHADD16 SHSUB16 SHADD8 SHSUB8 1 1 UQADD16 UQSUB16 UQADD8 UQSUB8 1 2 UHADD16 UHSUB16 UHADD8 UHSUB8 1 1 SSAT16 USAT16 1 Rn 1 SASX SSAX 1 1 UASX USAX 1 1 SXTAB SXTAB16 ...

Page 405: ...latency USAD8 1 Rn Rm 2a a Result latency is one fewer if the destination is the accumulate for a subsequent USADA8 USADA8 1 Rn Rm 2a Table C 8 Example interlocks Instruction sequence Behavior USAD8 R1 R2 R3 ADD R5 R6 R1 Takes three cycles because USAD8 has a Result Latency of two and the ADD requires the result of the USAD8 instruction USAD8 R1 R2 R3 MOV R9 R9 ADD R5 R6 R1 Takes three cycles The ...

Page 406: ...onal instruction for one cycle or two cycles if the instruction is a conditional multiply Flag setting multiplies followed by a flag setting instruction interlock the flag setting instruction for one cycle unless the instruction is a flag setting multiply in which case there is no interlock Table C 9 shows the cycle timing behavior of example multiply instructions Table C 9 Example multiply instru...

Page 407: ...t is used as the accumulate value for a subsequent multiply accumulate This only applies if the result is the same width as the accumulate value that is 32 or 64 bits SMLALD SMLALDX 1 Rn Rm 2 2 SMLSLD SMLSLDX 1 Rn Rm 2 2 UMAAL 2 Rn Rm RdLo RdHi 3 3 Table C 9 Example multiply instruction cycle timing behavior continued Example instruction Cycles Early Reg Late Reg Result latency ...

Page 408: ...tion to write the result to the destination register This additional cycle is not required if the divide instruction fails its condition code Result Latency for a UDIV instruction A divided by B is given by Result Latency for a SDIV instruction A divided by B is given by Note A divide instruction that fails its condition code or attempts to divide by zero has a Result Latency of three The value of...

Page 409: ...namic prediction 8 Incorrect dynamic prediction BX Rm b 1 Correct return stack prediction 9 Incorrect return stack prediction BX cond Rm b 1 Correct condition prediction and correct return stack prediction 8 Incorrect condition prediction 9 Correct condition prediction and incorrect return stack prediction BXJ cond Rm 1 Condition code fails 9 Condition code passes BLX Rm 9 BLX cond Rm 1 Condition ...

Page 410: ... the MSR MRS CPS and SETEND instructions Table C 11 shows processor state updating instructions and their cycle timing behavior Table C 11 Processor state updating instructions cycle timing behavior Instruction Cycles Comments MRS 1 All MRS instructions MSR 5 All other MSR instructions to the CPSR MSR SPSR 1 All MSR instructions to the SPSR CPS effect iflags 1 Interrupt masks only CPS effect iflag...

Page 411: ...tra cycle is required if the final address is potentially unaligned even if the final address turns out to be aligned PLD data preload hint instructions have cycle timing behavior as for load instructions Because they have no destination register the result latency is not applicable for such instructions For store instructions Rt is always a Late Reg Table C 13 shows the cycle timing behavior for ...

Page 412: ...hat is not a load or store double instruction or load or store multiple instruction For example with R2 aligned the following instruction sequence take three cycles to execute LDR cond pc sp imm 8 1 Conditional predicted incorrectly but return stack predicted correctly LDR cond pc sp cns 8 1 LDR pc addr_md_1cycle a 9 1 LDR pc addr_md_3cycle a 11 1 a See Table C 14 for an explanation of addr_md_1cy...

Page 414: ...addr_md_3cycle used in Table C 15 Table C 15 Load and Store Double instructions cycle timing behavior Example instruction Cycles Cycles with base writeback Memory cycles Result latency LDRD Result latency base register Address is doubleword aligned LDRD R0 R1 addr_md_1cycle a 1 2 1 2 2 2 LDRD R0 R1 addr_md_3cycle a 3 4 1 4 4 4 Address not doubleword aligned LDRD R0 R1 addr_md_1cycle a 2 2 2 2 3 2 ...

Page 415: ...ehavior of load and store multiples including the PC Note The Cycle timing behavior that Table C 17 shows also covers PUSH and POP instructions that behave like store and load multiple instructions with base register write back Table C 17 Cycle timing behavior of Load and Store Multiples other than load multiples including the PC Example instruction Cycles Cycles with base register write back Memo...

Page 416: ...les to execute STMIA R0 R1 R7 ADD R7 R10 R11 The following sequence has a result latency hidden by issue cycles It takes five cycles to execute LDMIA R0 R1 R7 ADD R10 R10 R3 The following sequence that has a POP instruction takes seven cycles to execute because R9 has a result latency of six cycles POP R1 R9 ADD R10 R10 R9 The following sequence that has a PUSH instruction takes five cycles to exe...

Page 417: ...r ARM DDI 0363G Copyright 2006 2011 ARM Limited All rights reserved C 23 ID073015 Non Confidential Note In the examples R0 and sp are 64 bit aligned addresses The instructions PUSH and POP always use the sp register for the base address ...

Page 418: ...eption and save exception return state respectively take one or two memory cycles depending on doubleword alignment first address location In all cases the base register is a Very Early Reg Table C 19 shows the cycle timing behavior for RFE and SRS instructions Table C 19 RFE and SRS instructions cycle timing behavior Example instruction Cycles Memory cycles Address doubleword aligned RFEIA Rn 10 ...

Page 419: ...le C 20 shows the synchronization instructions cycle timing behavior The synchronization instructions DMB DSB and ISB stall the pipeline for a variable number of cycles depending on the current state of the memory system Table C 20 Synchronization instructions cycle timing behavior Instruction Cycles Memory cycles Result latency CLREX 1 LDREX Rt Rn 1 1 2 LDREXB Rt Rn 1 1 2 LDREXH Rt Rn 1 1 2 LDREX...

Page 420: ...r The precise timing of coprocessor instructions is tightly linked with the behavior of the relevant coprocessor Table C 21 shows the coprocessor instructions cycle timing behavior Table C 21 shows the best case numbers Note Some instructions such as cache operations take more cycles Table C 21 Coprocessor instructions cycle timing behavior Instruction Cycles Result latency Comments MCR 6 MCR cond...

Page 421: ...n all cases the exception is taken in the Wr stage of the pipeline SVC and most Undefined instructions that fail their condition codes take one cycle A small number of Undefined instructions that fail their condition codes take two cycles Table C 22 shows the SVC BKPT Undefined prefetch aborted instructions cycle timing behavior Table C 22 SVC BKPT Undefined prefetch aborted instructions cycle tim...

Page 422: ...and No OPeration NOP instructions The DBG PLI SEV WFE and YIELD instructions are all treated the same as NOP and so have the same cycle timing behavior The WFI instruction stalls the pipeline for a variable number of cycles depending on the current state of the memory system Table C 23 IT and NOP instructions cycle timing behavior Example instructions Cycles Early Reg Late Reg Result latency Comme...

Page 423: ...cles to execute All transfers to and from the VFP system registers are also serializing This means that if there are any outstanding out of order completion VFP instructions the system register transfer instruction stalls in the iss stage until these instructions are complete VFP instructions that complete out of order are VMLA F32 VMLS F32 VNMLS F32 VNMLA F32 VDIV F32 VSQRT F32 VCVT F64 F32 and d...

Page 424: ...number of cycles and result latencies for single load and store instructions and load multiple instructions Values are shown for each instruction with and without base register writeback and with different starting address alignments Cycle counts and base register result latencies for store multiple instructions are the same as for the equivalent load multiple instruction Table C 25 Floating point...

Page 425: ...2 2 2 1 2 2 VLDM mode 32 Rn s1 s3 2 3 1 2 2 3 VLDM mode 32 Rn s1 s4 3 3 1 2 2 3 3 VLDM mode 64 Rn d1 2 2 2 2 VLDM mode 64 Rn d1 d2 3 3 2 3 3 VLDM mode 64 Rn d1 d3 4 4 2 3 4 4 VLDM mode 64 Rn d1 d4 5 5 2 3 4 5 5 Table C 25 Floating point load store instructions cycle timing behavior continued Example instruction Cycles memory cycles Cycles with writeback Result latency load Result latency base regi...

Page 426: ... and VNMLA F32 1b b VMLA F32 completes out of order and can take an extra cycle two in total if an add instruction VADD or certain dual issued instruction pairs are in the iss stage when the instruction completes Sn Sm 5c c Except when the instruction dependent on the result Sd is another VMLA F32 instruction and the dependent operand is the accumulate operand Sd In this case the result latency is...

Page 427: ...avior Table C 27 Floating point double precision data processing instructions cycle timing behavior Example instruction Cycles Early Reg Result latency VMLA F64 Dd Dn Dm a a Also VMLS F64 VNMLS F64 and VNMLA F64 13 Dn Dm 19 VADD F64 Dd Dn Dm b b Also VSUB F64 VMUL F64 and VNMUL F64 3 Dn Dm 9 VDIV F64 Dd Dn Dm 3 Dn Dm 96 VSQRT F64 Dd Dm 3 Dm 96 VMOV F64 Dd imm 1 1 VMOV F64 Dd Dm c c Also VABS F64 a...

Page 428: ...e instruction of the pair is interlocked both are interlocked This section describes Dual issue rules Permitted combinations on page C 35 C 23 1 Dual issue rules The following rules apply to dual issue instructions Both instructions must be available to the issue stage at the same time This is unlikely if there are many branches The second instruction must not use the PC as a source register unles...

Page 429: ...le precision CDP instructions VCVT F64 F32 and VMRS and VMSR Case B1 LDR Rt Rn imm c LDR Rt Rn Rm c LDR Rt Rn Rm LSL 1 2 or 3 c Any data processing instruction that does not require a shift by a register value d Any bitfield saturate or bit packing instruction e Any signed or unsigned extend instruction f Any SIMD add or subtract instruction g Other miscellaneous instructions h Case B1 Fb Any sing...

Page 430: ...HTB QADD QDADD QDSUB QSUB SBFX SSAT SSAT16 UBFX USAT and USAT16 f Signed or unsigned extend instructions are SXTAB SXTAB16 SXTAH SXTB SXTB16 SXTH UXTAB UXTAB16 UXTAH UXTB UXTB16 and UXTH g SIMD add and subtract instructions are QADD16 QADD8 QASX SQUB16 QSUB8 QSAX SADD16 SADD8 SASX SHADD16 SHADD8 SHASX SHSUB16 SHSUB8 SHSAX SSUB16 SSUB8 SSAX UADD16 UADD8 UASX UHADD16 UHADD8 UHASX UHSUB16 UHSUB8 UHSA...

Page 431: ...D 1 ID073015 Non Confidential Appendix D ECC Schemes This appendix describes some of the advantages and disadvantages of the different Error Checking and Correction ECC schemes for the TCMs It contains the following section ECC scheme selection guidelines on page D 2 ...

Page 432: ...sumption and can also lead to a decrease in performance Use the following guidelines to decide which scheme to use If you are in any doubt benchmark your system running typical software to find the best balance between area power and performance for your application For a TCM interface that contains mainly instructions use 64 bit ECC The vast majority of reads requested by the prefetch unit are do...

Page 433: ...nt mode description Power management on page 2 7 Clarified the description of Thumb 2 technology and Thumb instructions About the programmers model on page 3 2 Abort exceptions on page 8 9 Clarified byte invariant big endian format Byte invariant big endian format on page 3 4 Clarified little endian format Little endian format on page 3 4 nCPUHALT removed from timing diagram Figure 4 1 on page 4 2...

Page 434: ... the Instruction Set Attributes Register 3 Figure 4 21 on page 4 31 Table 4 17 on page 4 32 Clarified functions for bits 31 30 29 and 28 Table 4 24 on page 4 41 Clarified functions for bits 20 19 18 17 16 3 and 2 Table 4 25 on page 4 44 Clarified instructions that the PFU recognizes as procedure calls and procedure returns Return stack on page 5 5 Added reference to Application Note 204 Memory typ...

Page 435: ...bits 1 0 Table 4 33 on page 4 55 Added paragraph to clarify the error correction method used Error correction on page 8 6 Clarified description of using semaphores AXI slave interfaces for TCMs on page 8 17 Internal exclusive monitor on page 8 34 Updated combined issuing capability value for AXI master interface Table 9 1 on page 9 3 Clarified description of ARADDRS 22 3 TCM RAM access on page 9 2...

Page 436: ...l Register on page 4 63 Update instruction prefetch description Controlling instruction prefetch and program flow prediction on page 5 6 Update event bus interface description Event bus interface on page 6 19 Update description of store buffer draining Store buffer draining on page 8 19 Update AXI slave interface attributes AXI slave characteristics on page 9 22 Update Cache RAM access description...

Search results

Summary of Contents for Cortex-R4

Reviews:

Related manuals for Cortex-R4

Brands by name

Popular brands

ARM Cortex-R4, Technical Reference Manual

Search results

Summary of Contents for Cortex-R4

Reviews:

Related manuals for Cortex-R4

Brands by name

Popular brands