System Control
ARM DDI 0363G
Copyright © 2006-2011 ARM Limited. All rights reserved.
4-45
ID073015
Non-Confidential
[19]
DF2DI
F2_Id/F2_st/F2D dual issue control:
0
= Enabled. This is the reset value.
1
= Disabled.
[18]
DDI
0
= Enabled. This is the reset value.
1
= Disabled.
[17]
DOODPFP
Out-of-order Double Precision Floating Point instruction control:
0
= Enabled. This is the reset value.
1
= Disabled.
[16]
DOOFMACS
Out-of-order
FMACS
control:
0
= Enabled. This is the reset value.
1
= Disabled.
[15:14]
-
SBZ.
[13]
IXC
Floating-point inexact exception output mask::
c
0
= Mask floating-point inexact exception output. The output
FPIXC
is forced to zero. This
is the reset value.
1
= Propagate floating point inexact exception flag
FPSCR.IXC
to output
FPIXC
.
[12]
OFC
Floating-point overflow exception output mask:
0
= Mask floating-point overflow exception output. The output
FPOFC
is forced to zero. This
is the reset value.
1 = Propagate floating-point overflow exception flag
FPSCR.OFC
to output
FPOFC
.
[11]
UFC
Floating-point underflow exception output mask:
0
= Mask floating-point underflow exception output. The output
FPUFC
is forced to zero.
This is the reset value.
1
= Propagate floating-point underflow exception flag
FPSCR.UFC
to output
FPUFC
.
[10]
IOC
Floating-point invalid operation exception output mask:
0
= Mask floating-point invalid operation exception output. The output
FPIOC
is forced to
zero. This is the reset value.
1
= Propagate floating-point invalid operation exception flag
FPSCR.IOC
to output
FPIOC
.
[9]
DZC
Floating-point divide-by-zero exception output mask:
0
= Mask floating-point divide-by-zero exception output. The output
FPDZC
is forced to
zero. This is the reset value.
1
= Propagate floating-point divide-by-zero exception flag
FPSCR.DZC
to output
FPDZC
.
[8]
IDC
Floating-point input denormal exception output mask:
0
= Mask floating-point input denormal exception output. The output
FPIDC
is forced to
zero. This is the reset value.
1
= Propagate floating-point input denormal exception flag
FPSCR.IDC
to output
FPIDC
.
[7:4]
-
SBZ.
[3]
BTCMECC
Correction for internal ECC logic on BTCM ports:
d
0
= Enabled. This is the reset value.
1
= Disabled.
Table 4-25 Secondary Auxiliary Control Register bit assignments (continued)
Bits
Name
Function