Events and Performance Monitor
ARM DDI 0363G
Copyright © 2006-2011 ARM Limited. All rights reserved.
6-17
ID073015
Non-Confidential
Figure 6-9 PMINTENSET Register bit assignments
shows the PMINTENSET bit assignments.
Reading this register returns the current setting, with a 1 in one of the counter bits indicating that
interrupts are enabled for that counter. Writing a 1 to a particular interrupt bit enables interrupt
generation on overflow of that counter. Writing a 0 has no effect. You can only disable interrupts
by writing to the PMINTENCLR Register.
To access the PMINTENSET Register, read or write CP15 with:
MRC p15, 0, <Rd>, c9, c14, 1 ; Read
PMINTENSET Register
MCR p15, 0, <Rd>, c9, c14, 1 ; Write PMINTENSET Register
If this unit generates an interrupt, the processor asserts the pin
nPMUIRQ
. You can route this
pin to an external interrupt controller for prioritization and masking. This is the only mechanism
that signals this interrupt to the processor.
Note
ARM expects that the Performance Monitor interrupt request signal,
nPMUIRQ
, connects to a
system interrupt controller.
6.3.12
c9, Interrupt Enable Clear Register
The PMINTENCLR Register characteristics are:
Purpose
Determines if any of the PMXEVCNTR Registers,
PMXEVCNTR0-PMXEVCNTR2 and PMCCNTR, generate an interrupt
request on overflow.
Usage constraints
The PMINTENCLR Register is:
•
a read/write register
•
accessible in Privileged mode only.
Configurations
Available in all processor configurations.
Attributes
C
31
3 2 1 0
Reserved
P2
P1
P0
Performance monitor counter
overflow interrupt enables
Cycle count overflow interrupt enable
Table 6-10 PMINTENSET Register bit assignments
Bits
Name
Function
[31]
C
PMCCNTR overflow interrupt
[30:3]
-
UNP on reads, SBZP on write
[2]
P2
PMC2 overflow interrupt
[1]
P1
PMC1 overflow interrupt
[0]
P0
PMC0 overflow interrupt