Level Two Interface
ARM DDI 0363G
Copyright © 2006-2011 ARM Limited. All rights reserved.
9-16
ID073015
Non-Confidential
shows possible values of
AWADDRM
,
AWBURSTM
,
AWSIZEM
, and
AWLENM
for an
STR
or an
STM
that transfers one register, an
STM
1, to Normal memory through
the AXI master port.
9.3.7
AXI transaction splitting
The processor splits AXI bursts when it accesses addresses across a cache line boundary, that
is, a 32-byte boundary. An instruction that accesses memory across one or two 32-byte
boundaries generates two or three AXI bursts respectively. The following examples show this
behavior. They are provided as examples only, and are not an exhaustive description of the AXI
transactions. Depending on the state of the processor, and the timing of the accesses, the actual
bursts generated might have a different size and length to the examples shown, even for the same
instruction.
For example,
LDMIA R10, {R0-R5}
loads six words from memory. The number of AXI
transactions generated by this instruction depends on the base address, R10:
•
If all six words are in the same cache line, there is a single AXI transaction. For example,
for
LDMIA R10, {R0-R5}
with
R10 = 0x1008
, the interface might generate a burst of three,
64-bit read transfers, as shown in
.
Table 9-18 STR or STM1 to cacheable write-through or Non-cacheable Normal memory
Address[2:0]
AWADDRM
AWBURSTM
AWSIZEM
AWLENM
WSTRBM
0x0
(byte 0) (word 0)
0x00
Incr
32-bit
1 data transfer
b00001111
0x1
(byte 1)
0x01
Incr
64-bit
1 data transfer
b00011110
0x2
(byte 2)
0x00
Incr
64-bit
1 data transfer
b00111100
0x3
(byte 3)
0x03
Incr
64-bit
2 data transfers
b01111000
b00000000
0x4
(byte 4) (word 1)
0x04
Incr
32-bit
1 data transfer
b11110000
0x5
(byte 5)
0x05
Incr
32-bit
2 data transfers
b11100000
b00000001
0x6
(byte 6)
0x06
0x08
Incr
Incr
16-bit
16-bit
1 data transfer
1 data transfer
b11000000
b00000011
0x7
(byte 7)
0x04
Incr
32-bit
2 data transfers
b10000000
b00000111
Table 9-19 AXI transaction splitting, all six words in same cache line
ARADDRM
ARBURSTM
ARSIZEM
ARLENM
0x1008
Incr
64-bit
3 data transfers