Alstom SHPM 101, Service Manual

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SERVICE MANUAL R5888C
QUADRAMHO Chapter 2
Page 22 of 74
d) runs the BAR drop off timer.
e) sets various output register flags.
f) re-enables Zone 1 interrupt feature after previous interrupt has been terminated.
g) sends a master reset pulse to the comparators after an “All Poles Dead”
condition is detected.
4.9.39 EXOP subroutine
This subroutine performs several functions, these are listed below:
a) clearing and latching of the scheme logic indications
b) runs the comparator self check routine.
4.9.40 ENF subroutine
The ENF subroutine performs the band pass switching logic. This logic is used to
improve performance of the relay and is explained in Sections 4.2 and 5.16.18.
4.9.41 OP subroutine
The OP subroutine transfers the data that is stored in the output registers to the
correct output ports.
The OP subroutine also runs a test to determine if the timer interrupt is running;
if not, the interrupt is re-enabled.
4.9.42 LTIM timer interrupt routine
The timer interrupt is an internal interrupt that is generated within the
microcontroller. The digital synchronous polarising and software timers are
contained within the timer interrupt routine.
The timer interrupt occurs at regular intervals of approximately 179
µ
s.
The synchronous polarising is serviced on every timer interrupt which gives a
resolution (jitter) of the memory output V
MC
of
±
3.2
°
(for a detailed description of
the memory see Section 5.2.2).
The timers are serviced in six groups which contain two or three timers.
Each group of timers is serviced once in every eleven timer interrupts which gives a
timer resolution of 11 x 179.44 = 1.974ms.
4.9.43 Basic interrupt principle
When an external or timer interrupt request is made, the main loop continues
executing the current instruction. After this has finished, the address of the next
instruction to be executed within the main loop is stored automatically by the
microcontroller. The interrupt routine is then entered and the data being processed
within the main loop at the point of interrupt is then stored temporarily. This allows
restoration of data when the interrupt returns from the main loop. Normally the
interrupt returns to the address stored when the interrupt occurred. This is true for
the timer interrupt, but within the scheme logic the external (Zone 1) interrupt is
sometimes ‘forced’ to return to the beginning of the loop (See Section Z1 INT
routine).
4.9.44 Principle of timer operation
There are 16 timer interrupt timers which all operate using the same principle.
The basic operation is as follows. Four internal microcontroller registers are
allocated for use by the timers, two of these are designated timer start registers
(TSR) which contain 16 timer start bits (one for each timer). Similarly the other two