Alstom SHPM 101, Service Manual

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SERVICE MANUAL R5888C
QUADRAMHO Chapter 2
Page 9 of 74
signals are squared up and level shifted to generate the (V –
I
Z) signals.
These form one input to the comparator. Three additional squaring amplifiers are
required to generate three phase phase
I
Z square waves. These are used in the
directional line for the phase-phase elements.
The guard zone for the quadrilateral version requires a forward setting which is
twice that of the Z1 ground fault setting. This is obtained by attenuating the Z1
voltages, after the Z1/Z1X selector, by a factor of two, mixing with the
appropriate
I
Z signal and squaring to produce three (V –
I
Z) square waves.
4.7.2 Comparator board ZH0731
A block diagram for the mho version of this board is shown in Figure13 and for
the quadrilateral version in Figure14. The functions of the left hand board of this
module are as follows:
a) The clock signals
A total of seven clocks at different frequencies are required by the various circuits
(ie. level detectors, polarising and comparators). These are all derived from one
clock, labelled MCK, by a number of divider circuits.
The main clock is divided by 4, 5 and 8 to derive three other frequencies, and a
further three are generated on the level detector board. As part of the continuous
monitoring of the relay MCK/5 and MCK/8 are monitored, and an alarm given if
either should fail.
b) The polarising circuits
The polarising signals required for the shaped mho characteristics are described in
Section 5.2.2. They consist of mixing the three phase-neutral voltages and the
memory signals and digitally phase shifting. The exact proportions are given in
Section 5.2.1. The memory is described in Section 5.2.2.
When the memory is not
available it is replaced with a small percentage of the
I
Z signal. This provides a
restraining influence in the polarising for close-up three phase faults after the
memory has expired. This prevents operation of Z1 and Z2 elements for close-up 3
phase reverse faults.
c) Comparators
The comparators required for Z1 and Z2 are located on this board.
The principle on which the sequence comparator operates is described in
Section 5.1. The comparator is implemented in a customer designed ULA
(uncommitted logic array). Each ULA contains two main comparators and two
inhibit comparators as shown in Figure15. In addition, each ULA has nine
inhibit inputs which when active, force a main comparator to restrain.
Inhibits 1 – 4 act on main comparator 1, inhibits 8 – 9 on main comparator 2,
and inhibits 5 – 7 are common to both.
Two clocks (MCK and MCK/5) are required and the two main comparators
may be reset by a signal from the scheme logic (MRI). Each ULA has a self
checking feature controlled by the scheme logic using inputs SC and MRI.
This is described in Section 6.23. The twelve comparators required for Z1 and
Z2 are arranged as shown in Figure 16. Each ULA is used for a ground fault
element and a phase-phase fault element. One inhibit comparator per ULA is
used for a directional line. The quadrilateral version also requires the two side
lines as described in Section 5.5. The remaining inhibit comparators are used
for this. The side lines are also sent to the Z3 comparators. The additional
circuits required to generate the guard zone logic are described in Section 5.6.