Alstom SHPM 101, Service Manual

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SERVICE MANUAL R5888C
QUADRAMHO Chapter 2
Page 18 of 74
The input levels to operate the level detectors are as follows:
50Hz (47 – 51) P/U = 10.1 – 14.0% of rated current at reference setting
60Hz (56 – 61) P/U = 10.7 – 15.2% of rated current at reference
The high set current level detector lowest setting (tolerance) is designed to be 10%
greater than the highest pick up level of the low set current level detector.
4.9.22 Power swing blocking hardware
The power swing blocking hardware consists of the ninth LED, the 4 way switch
bank and associated drive circuitry. The switch bank function is to allow the
blocking signal produced by the scheme logic processor board to be routed
though to the correct comparators by selection of the appropriate switch.
4.9.23 Scheme logic software
The complete software for Quadramho is contained in a 2732A EPROM
(4k x 8 bit). This allows changes to be made to suit individual customer
requirements.
There is only 1 version of software which is standard for all Quadramho versions.
The software used in Quadramho is constructed in modular form in which each
subroutine performs individual, or groups, of well defined functions. This allows
changes to be made to specified areas of program without complication.
All main subroutines within the scheme logic are common for all schemes.
However, the option subroutine (OPT) will use additional routines depending on the
scheme selected. The main program loop is shown in Figure 25.
4.9.24 INIT subroutine
After a hardware reset has occurred the microcontroller executes an initialisation
routine called INIT. It should be noted that the INIT routine is only run once.
The operations performed by this routine are shown below:
a) Allows a set time for all components to “settle down”
b) Sets the PPI to the correct mode of operation (see Section 4.9.10).
c) Sets microcontroller ports so that input data can be read.
d) Sends a master reset pulse (MRI) to reset all comparator elements.
e) Initialises all internal microcontroller memory.
f) Enables timer and external Zone 1 interrupts.
g) Initialises inoperative alarm and code switch monitor circuits (See Section
4.9.15).
h) Sets the self check registers to indicate that a self check has not yet taken place
(see test options Section 4.9.46).
4.9.25 The main loop
After the initialisation procedure has been performed the main loop is then
executed by the microcontroller
The general operation principle of the main loop is as follows:
Firstly all input ports and switch banks are read by the microcontroller at the
beginning of the loop and then stored in registers which are designated as input
registers. This data is then processed by subroutines within the main loop which,
depending on these inputs, set bits in registers that are designated output registers.