Alstom SHPM 101, Service Manual

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SERVICE MANUAL R5888C
QUADRAMHO Chapter 2
Page 39 of 74
Phase C voltage is used as a reference signal for pre-fault phase information, after
being squared by a high gain amplifier. The length of one half cycle is measured
in units of 179
µ
s (the timer interrupt period of the microprocessor scheme logic)
and the number of units is stored in a register. When this half cycle finishes, the
carousel is rotated anti-clockwise by one register and the length of the next half
cycle measured and stored. This process continues indefinitely, with new data
overwriting the old when all 32 registers are full.
To generate the synchronous polarising output signal, an examination is made of
the data held in the 8th register anti-clockwise from the present input register.
This number is then used to determine the length of the output half cycle required.
When the output half cycle has been produced the polarity of the output is
reversed and another examination is made of the data held in the register which is
at the present 8th position. The next half cycle is generated accordingly.
This process is repeated indefinitely, producing the synchronous polarising output
wave.
This method allows the reproduction of the frequency of the input signal V
C
.
The output is phase locked with the input by effectively adjusting the number in the
output register by plus or minus one, every fourth output edge, to bring the output
into phase with V
C
as closely as possible.
When any voltage level detector resets or any comparator operates, this is deemed
to be a faulty or dead line condition and the memory is allowed to run out.
Under these circumstances, the direction of rotation of the carousel is reversed
(See Figure 45) and the output is maintained from data previously stored, for 16
half cycles, after which the synchronous polarising output is disconnected from the
polarising mixing circuits. The data in the most recently recorded registers are not
used, because distorted voltage may be present in the period just before the
voltage level detector resets, or the comparator operates. During the 16 half cycles
of memory run-out, the phase lock is disabled to protect the synchronous polarising
from any undesirable change in frequency.
A period of 140ms is allowed, after all voltage level detectors become operated
and all comparators are reset, before the synchronous polarising is reconnected.
This period allows the registers to fill with healthy phase information. Immediately
before the 140ms expires, a comparison is made between the number in the
current input register (equivalent to the elapsed time of the current half cycle) and
the number in the next anti-clockwise register (equivalent to the length of the
previous half cycle) The difference in time is effectively put into the output register,
so that when the synchronous polarising is reconnected, the output is immediately
in phase with the input. At this instant of reconnection, several cycles of accurate
synchronous polarising are already available for Zone 1 comparator operation,
this being an advantage over other methods.
The synchronous polarising signals for the A and B phases are obtained from V
MC
by phase shifting.
5.3 Offset MHO characteristic
The offset mho characteristic for Zone 3 is produced by the same type of phase
comparator as for Zones 1 and 2, but using different input quantities as shown in
Figure 46 ie:
A1 = V–
I
Z
B1 = (V+
I
Z) /–90
°