Chapter 3
81
Theory of Operation
Theory of Operation
T
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Multiple Module Synchronous Trigger Timing
Triggers are registered into the N6030A using the SYNC clock. The SYNC
clock is nominally at the sample clock frequency divided by 8. However at
lower sample rates an internal variable modulus prescaler selects other
binary divide ratios: 8, 4, 2, and 1.
Multiple ARB synchronization is only supported in the 625 MHz – 1.25
GHz frequency range. The input clock frequency ranges and prescaler divide
ratios are as specified in
Table 3-2
.It is necessary to insure that the correct
timing relationships are achieved to guarantee consistent synchronous
trigger operation. The trigger input must occur within a valid window with
respect to the SYNC clock. The window is specified by two times:
Twin_low -- the minimum trigger delay after the prior SYNC clock edge;
and Twin_high -- the minimum trigger setup before the next SYNC clock
edge. These are specified for the trigger Input relative to the SYNC clock
Output. The trigger must be a minimum of two SYNC clock cycles long.
The trigger timing is specified relative to the rising edge of the SYNC clock
by default, as shown in
Figure 3-8
. To guarantee proper synchronous trigger
operation with arbitrary length cables, it is possible to configure the trigger
inputs to register the trigger event with respect to the falling edge of the
SYNC clock, under software control. In this way there is always a setting for
the trigger input timing which will operate reliably for any chosen cable. The
typical specifications for the trigger window using the internal clock at 1.25
GS/s is (these values will vary at other clock frequencies):
Twin_high > 3.4 ns
Twin_low > -2.8 ns (the trigger can occur slightly before the prior
SYNC clock edge)
Table 3-2 SYNC Clock Frequency Ranges
Frequency Range
SYNC Clock Prescaler Divide Ratio
625 MHz-1.25 GHz
8
312.5 MHz-625 MHz
Multi-Module Synchronization
Not Supported
156.25 MHz-312.5 MHz
100 MHz-156.25 MHz
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