2200.
Vertical Adjust
Vertical adjustment defines the
difference in the SYNC IN VSYNC
and output VSYNC. Typically,
this should be in the range of 0
to +1 frame in lines. For
example, a 1080I output could
be adjusted from 0 to 1125.
0 - 1125
Pixel Phase
Pixel Phase adjustment is a very
fine grain adjustment that can
adjust within a single clock. The
increments are 1/64th of a clock.
The valid range is 0 to 63.
0 - 63
Genlock Status
Shows if GENLOCK input is
currently being used for the
decoder or in FREE RUN mode
Genlock CVBS
Out
This configuration is used
generally with 3D applications.
The ‘MASTER’ unit CVBS
configuration must be configured
as ‘SYNC’.
VIDEO - CVBS output is video
SYNC - CVBS output is black burst
sync signal
Genlock Reset
Reinitializes the Genlock System.
27
Summary of Contents for RD-71
Page 1: ...RD 71 10 bit 1080P Integrated Receiver Decoder USER GUIDE v2 02 10 1 ...
Page 5: ...Application Diagrams Turn Around and Service Filtering 5 ...
Page 6: ...Zixi IP Transport Zixi Link point to point or Zixi Receive point to multi point 6 ...
Page 9: ...6 NC No Connect 7 GND Ground 8 L Left 9 R Right 9 ...
Page 32: ...32 ...
Page 45: ...RF Params LB model 45 ...
Page 56: ...Bars Tones and ID 56 ...
Page 101: ...101 ...
Page 109: ...109 ...
