8-38
IM 704420-01E
Status Byte Operation
A service request is issued when bit 6 of the status
byte becomes a “
1
.” Bit 6 is set to “
1
” when any of the
other bits becomes a “
1
” (when the corresponding bit
of the service request enable register is also set to “
1
”).
For example, if an event occurs and the logical AND of
the standard event register and the corresponding
enable register becomes a “
1
”, then bit 5 (ESB) is set
to “
1
.” At this point, if bit 5 of the service request
enable register is “
1
,” then bit 6 (MSS) is set to “
1
”
causing the instrument to request service from the
controller.
In addition, you can also check what type of event
occurred by reading the contents of the status byte.
Reading the Status Byte
The following two methods are available in reading the
contents of the status byte.
Query using the *STB? command
An
*STB?
query causes bit 6 to be a MSS bit.
Therefore, the MSS bit is read. No bits in the status
byte are cleared after reading the status byte.
Serial polling
Serial polling causes bit 6 to be a RQS bit.
Therefore, the RQS bit is read. After reading the
status byte, only the RQS bit is cleared. You cannot
read the MSS bit when serial polling is used.
Clearing the Status Byte
There are no methods available that can forcibly clear
all the bits of the status byte. The bits that are cleared
for each operation are shown below.
When a query is made using the *STB? command
None of the bits are cleared.
When serial polling is executed
Only the
RQS
bit is cleared.
When an *CLS command is received
Receiving the
*CLS
command will not clear the
status byte itself, but the contents of the standard
event register that affect the status byte. As a
result, the corresponding bit of the status byte is
cleared. Since the
*CLS
command does not clear
the output queue, bit 4 (MAV) of the status byte is
unaffected. However, if the
*CLS
command is
received immediately after the program message
terminator, the output queue is also cleared.
8.8.3 Standard Event Register
Standard Event Register
URQ
6
PON
7
5
4
3
2
1
0
CME EXE DDE QYERQCOPC
Bit 7 PON (Power ON)
Set to “
1
” when the instrument is turned ON.
Bit 6 URQ (User Request)
Not used (always 0)
Bit 5 CME (Command Error)
Set to “
1
” when there is an error in the command
syntax.
Example;
Misspelling of a command name, “
9
” exists in octal
data.
Bit 4 EXE (Execution Error)
Set to “
1
” when the command syntax is correct, but
the command cannot be executed in the current
state of the instrument.
Example;
Parameter outside the range.
Bit 3 DDE (Device Dependent Error)
Set to “
1
” when a command cannot be executed for
internal reasons other than a command syntax error
and command execution error.
Bit 2 QYE (Query Error)
Set to “
1
” when a query command is transmitted,
but the error queue is empty or the data are lost.
Example;
No response data, output queue overflowed and
data were lost.
Bit 1 RQC (Request Control)
Not used (always 0)
Bit 0 OPC (Operation Complete)
Set to “
1
” when the operation specified by the
*OPC
command (see section 8.7) has been completed.
Bit Masking
If you wish to mask a certain bit of the standard event
register so that it does not cause bit 5 (ESB) of the
status byte to change, set the corresponding bit of the
standard event enable register to “
0
.”
For example, to mask bit 2 (QYE) so that the ESB bit is
not set to “
1
” when a query error occurs, set bit 2 of the
standard event enable register to “
0
.” This is done
using the
*ESE
command. The
*ESE?
request
command can be used to query the standard event
enable register to check whether each bit is set to “
1
”
or “
0
.” For details on the
*ESE
command, see section
8.7.
8.8 Status Report
