Xilinx Virtex UltraScale+ FPGAs, Руководство пользователя

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Proprietary Backplane Protocols with FEC up to 58 Gb/s
FEC can be enabled in 50G raw mode (with or without scrambling).
TX Buffer
The GTM transceiver TX datapath has two internal parallel clock domains used in the PCS: the
interface with PMA parallel clock domian (XCLK), and the PCS internal clock domain
(TXUSRCLK). To transmit data, the TX buffer provides data width conversion between these
clock domains when necessary, depending on the operating data width and encoding mode. The
following figure shows the TX datapath clock domains.
Figure 30:
TX Clock Domains
Pattern
Generator
Polarity
TX
FIFO
To RX Parallel Data
(Near-End PCS Loopback)
From RX Parallel Data
(Far-End PCS Loopback)
FEC
Gray
Encoder
TX PCS
PISO
TX
Driver
TX
Pre/
Pre
2/
Post
Emp
TX PMA
TX
Interface
TX Serial Clock PMA Parallel Clock (XCLK) PCS Parallel Clock (TXUSRCLK)
Device Parallel
Clock
(TXUSRCLK2)
X20914-053018
Pre-
Coder
The GTM transmitter includes a TX FIFO to support data width conversion when data crosses
from TXUSRCLK to XCLK domain, and the table below shows the possible scenarios. The buffer
does not tolerate ppm differences, and only provides phase compensation between the two
clocks. The TX buffer inside the GTM transceiver must always be used. Buffer bypass is not
allowed.
Table 34: TX FIFO Data Width Conversion Scenarios
PCS Parallel Clock (TXUSRCLK)
Domain Data Width
PMA Parallel Clock (XCLK) Domain
Data Width
FEC Support
64-bit 64-bit No
80-bit 128-bit Yes
128-bit 128-bit No
Chapter 3: Transmitter
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex Ult GTM Transceivers 66
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