Xilinx Virtex UltraScale+ FPGAs, Руководство пользователя

Страница: 43 / 145

Table 19: Recommended Receiver Resets for Common Situations (cont'd)
Situation
Components
to be Reset
Recommended RX Reset Setting
RXRESETMODE RXPMARESETMASK RXPCSRESETMASK
1
After connecting RXN/RXP Entire RX
2'b00 8’b11111111 4’b1111
After recovered clock
becomes stable
RX PCS
2'b11 8’b00000000 4’b1111
After RX elastic buffer error RX PCS
2'b11 8’b00000000 4’b1111
After PRBS error
PRBS Error
Counter
2'b11 8’b00000000 4’b1000
Eye Scan reset only Eye Scan
2'b11 8’b00000000 4’b0001
Notes:
1.
RXPCSRESETMASK[1] can be set to 0 if the FEC is bypassed.
After Power-up and Configuration
The PLL being used and the entire GTM RX require a reset after configuration. See GTM
Transceiver RX Reset in Response to Completion of Configuration .
After Turning on a Reference Clock to the PLL Being
Used
If the reference clock(s) changes or GTM transceiver(s) are powered up after configuration,
perform a full RX sequential reset after the PLL fully completes its reset procedure.
After Changing the Reference Clock to the PLL Being
Used
Whenever the reference clock input to the PLL is changed, the PLL must be reset afterwards to
ensure that it locks to the new frequency. Perform a full RX sequential reset after the PLL fully
completes its reset procedure.
After Assertion/Deassertion of PLLPD for the PLL
Being Used
When the PLL being used goes back to normal operation after power down, the PLL must be
reset. Perform a full RX sequential reset after the PLL fully completes its reset procedure.
After Assertion/Deassertion of RXPD
After the RXPD signal is deasserted, perform a full RX sequential reset.
Chapter 2: Shared Features
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex Ult GTM Transceivers 43
Send Feedback