93
SLUUBD3D – September 2015 – Revised September 2018
Copyright © 2015–2018, Texas Instruments Incorporated
Communications
Chapter 16
SLUUBD3D – September 2015 – Revised September 2018
Communications
16.1 Introduction
The bq78350-R1 uses SMBus v1.1 with MASTER mode and packet error checking (PEC) options per the
SBS specification.
16.2 SMBus On and Off State
The bq78350-R1 detects an SMBus off state when SMBC and SMBD are logic-low for
≥
2 seconds.
Clearing this state requires either SMBC or SMBD to transition high. Within 1 ms, the communication bus
is available.
16.3 Packet Error Checking
The bq78350-R1 can receive or transmit data with or without packet error checking (PEC).
In the write-word protocol, if the host does not support PEC, the last byte of data is followed by a stop
condition and the
[HPE]
bit should be set to 0 (default).
In the write-word protocol, the bq78350-R1 receives the PEC after the last byte of data from the host. If
the host does not support PEC, the last byte of data is followed by a stop condition. After receipt of the
PEC, the bq78350-R1 compares the value to its calculation. If the PEC is correct, the bq78350-R1
responds with an ACKNOWLEDGE. If it is not correct, the bq78350-R1 responds with a NOT
ACKNOWLEDGE and sets an error code. If the host supports PEC, the
[HPE]
bit should be set to 1.
In the read-word and block-read in MASTER mode, the host generates an ACKNOWLEDGE after the last
byte of data sent by the bq78350-R1. The bq78350-R1 then sends the PEC, and the host, acting as a
master-receiver, generates a NOT ACKNOWLEDGE and a stop condition.
16.4 Slave Address
The bq78350-R1 has a configurable addressing scheme that can be enabled or this feature can be
disabled resulting in the slave address being fixed as 0x16/0x17.
When
[FIXED_ADDR]
in
SMB Configuration
is clear (0), then the slave address is determined by the
voltage measured at the SMBA pin. The voltage on the SMBA pin is created via either being tied to VCC,
VSS, or through an external resistor divider. The external divider can be enabled and disabled via the
ADREN (pin 29) and an external FET. The upper resistor should be connected between VCC and SMBA
with the lower resistor of the divider connected between SMBA and VSS. Both of these resistors are
recommended to be 1% tolerance or better.
Upon exit from Power On Reset (POR) or when
OperationStatus() [PRES]
transitions from 0 to 1, the
bq78350-R1 drives ADREN high, takes a number of sequential voltage measurements (set by
Addr
Reads
) of the SMBA pin taking approximately 32 ms each. The corresponding address, set by
SMBTAR_ADDR0…7
, is determined for each measurement with the most common address selection
being the one used. If all are different, then the average voltage value is used to determine the address.
Upon completion of the address selection, ADREN is set low to turn off the resistor divider to conserve
power.
Care should be taken in the setting of
Addr Reads
as the bq78350-R1 will only respond to address
0x16/0x17 until at least
Addr Read
× 32 ms after POR.
The actual address corresponding to the SMBA voltage is configurable per the following table.
