Chapter 6
Clock Generation
The FE310-G000 supports many alternative clock-generation schemes to match application
needs. This chapter describes the structure of the clock generation system. The various clock
configuration registers live either in the AON block (Chapter 12) or the PRCI block (Section 6.2).
6.1
Clock Generation Overview
Figure 2:
FE310-G000 clock generation scheme
Figure 2 shows an overview of the FE310-G000 clock generation scheme. Most digital clocks
on the chip are divided down from a central high-frequency clock
hfclk
produced from either
the PLL or an on-chip trimmable oscillator. The PLL can be driven from either the on-chip oscil-
SiFive FE310-G000 Manual: v3p2
© SiFive, Inc.
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