Preface
iv
7UM62 Manual
C53000-G1176-C149-3
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I
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1706
I2>>
0
T
S
R
Q
Input signals of dynamic quantity
Formation of one output signal from a number
of analog inputs
Timer (dropout delayed)
Limit stage with parameter address and
T
Dynamic triggered pulse timer (monoflop)
Static memory (RS–flipflop) with setting input (S),
=1
Exclusive–OR gate: output is active, if only one
of the inputs is active
=
Coincidence gate: output is active, if both
inputs
are active simultaneously
0
T
1706
T I2>>
Timer (pick up delayed) with parameter address
and designator
resetting input (R), output (Q) and inverted
Q
designator
output (Q)