UP-5900VS
CIRCUIT DESCRIPTION
5 – 29
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OTHER SYSTEM AND TEST SIGNALS
GPO15
SUSB#
SUSB#
GENCFG
Bit 17
Not available as GPO if using for power management.
GPO16
SUSC#
SUSC#
GENCFG
Bit 17
Not available as GPO if using for power management.
GPO17
CPU_STP#
CPU_STP#
GENCFG
Bit 18
Not available as GPO if using for clock control.
GPO18
PCI_STP#
PCI_STP#
GENCFG
Bit 19
Not available as GPO if using for clock control.
GPO19
ZZ
ZZ
GENCFG
Bit 20
Not available as GPO if using for power management.
GPO20
SUS_STAT1#
SUS_STAT1#
GENCFG
Bit 21
Not available as GPO if using for power management.
GPO21
SUS_STAT2#
SUS_STAT2#
GENCFG
Bit 22
Not available as GPO if using for power management.
GPO22
XDIR#
XDIR#
GENCFG
Bit 28
Not available as GPO if using X-bus transceiver.
GPO23
XOE#
XOE#
GENCFG
Bit 28
Not available as GPO if using X-bus transceiver.
GPO24
RTCCS#
RTCCS#
GENCFG
Bit 29
Not available as GPO if using external RTC that doesn’t do self
decode.
GPO25
RTCALE
RTCALE
GENCFG
Bit 30
Not available as GPO if using external RTC that doesn’t do self
decode.
GPO26
KBCCS#
KBCCS#
GENCFG
Bit 31
Not available as GPO if using external KBC that doesn’t do self
decode.
GPO[27:28]
GPO
Non-multiplexed GPOs which are always available.
GPO29
IRQ9OUT#
GPO
XBCS
Bit 8
Not available as GPO if using external APIC. This signal is used
for IRQ9 output in APIC mode, where it is level triggered, active
low.
GPO30
GPO
Non-multiplexed GPO which is always available.
Name
Type
Description
CONFIG1
I
CONFIGURATION SELECT 1. This input signal is used to select the type of microprocessor being used in the sys-
tem. If CONFIG1=0, the system contains a Pentium microprocessor. If CONFIG1=1, the system contains a Pentium
II microprocessor. It is used to control the polarity of INIT and CPURST signals.
CONFIG2
I
CONFIGURATION SELECT 2. This input signal is used to select the positive or subtractive decode of FFFF0000h
FFFFFFFFh memory address range (top 64 Kbytes). If CONFIG[2]=0, the PIIX4E will positively decode this range. If
CONFIG[2]=1, the PIIX4E will decode this range with subtractive decode timings only.
The input value of this pin must be static and may not dynamically change during system operations.
PWROK
I
POWER OK. When asserted, PWROK is an indication to PIIX4E that power and PCICLK have been stable for at
least 1 ms. PWROK can be driven asynchronously.
When PWROK is negated, PIIX4E asserts CPURST, PCIRST# and RSTDRV. When PWROK is driven active
(high), PIIX4E negates CPURST, PCIRST#, and RSTDRV.
SPKR
O
SPEAKER. The SPKR signal is the output of counter timer 2 and is internally “ANDed” with Port 061h bit 1 to pro-
vide the Speaker Data Enable. This signal drives an external speaker driver device, which in turn drives the ISA sys-
tem speaker.
During Reset: Low
After Reset: Low
During POS: Last State
TEST#
I
TEST MODE SELECT. The test signal is used to select various test modes of PIIX4E. This signal must be pulled up
to VCC(SUS) for normal operation.
Signal Name
Multiplexed With
Default
Control Register and Bit
(PCI Function 1)
Notes
Содержание UP-5900
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