UP-5900VS
CIRCUIT DESCRIPTION
5 – 49
4) POWER PINS
5) LED INTERFACE
6) ATTACHMENT UNIT INTERFACE
7) TEST AND THE OTHER PINS
MD0-7
I/O
108, 107, 105-100
Boot PROM data bus
ROMCSB
O
110
ROM Chip Select: This is the chip select signal of the Boot PROM.
OEB
O
88
Output Enable: This enables the output buffer of the Boot PROM or Flash memory during a read
operation.
WEB
O
89
Write Enable: This signal strobes data into the Flash memory during a write cycle.
Symbol
Type
Pin No
Description
Symbol
Type
Pin No
Description
VDD
P
1, 12, 25, 35, 46, 58,
59, 77, 90, 96, 106,
109, 119
+3.3V
GND
P
7, 18, 30, 40, 55, 56,
62, 74, 80, 85, 93,
111, 112, 113, 124
Ground
Symbol
Type
Pin No
Description
LED0, 1, 2
O
99, 98, 97
LED pins
LEDS1-0
00
01
10
11
LED0
TX/RX
TX/RX
TX
TX
LED1
LINK100
LINK10/100
LINK10/100
LINK100
LED2
LINK10
FULL
RX
LINK10
During power down mode, the LED’s are OFF.
Symbol
Type
Pin No
Description
TXD+
TXD-
O
O
92
91
100/10BASE-T transmit (Tx) data.
RXIN+
RXIN-
I
I
87
86
100/10BASE-T receive (Rx) data.
X1
I
79
25 MHz crystal/OSC. input.
X2
O
78
Crystal feedback output. This output is used in crystal connection only.
It must be left open when X1 is driven with an external 25 MHz oscillator.
Symbol
Type
Pin No
Description
RTT2-3
TEST
81, 82
Chip test pins.
RTSET
I/O
84
This pin must pull low by 1.8KW resistor.
NC
–
54, 71, 72, 73, 94
Reserved
Содержание UP-5900
Страница 128: ...UP 5900VS PWB LAYOUT 10 1 CHAPTER 10 PWB LAYOUT MAIN PWB UPPER SIDE ...
Страница 129: ...UP 5900VS PWB LAYOUT 10 2 BOTTOM SIDE ...
Страница 130: ...UP 5900VS PWB LAYOUT 10 3 INVERTER PWB UPPER SIDE BOTTOM SIDE UPPER SIDE UPPER SIDE BOTTOM SIDE ...
Страница 131: ...UP 5900VS PWB LAYOUT 10 4 UPPER SIDE BOTTOM SIDE UPPER SIDE BOTTOM SIDE ...