UP-5900VS
CIRCUIT DESCRIPTION
5 – 44
3) When a card has been scanned, interrupts for the MCR interface
are activated.
4) The main CPU reads taken card data from the FIFO buffer in the
interrupt handling. The main CPU can read the data using IN com-
mand of 0WAIT.
Even after the LCR which is the last character of a card was read,
10 to 20 characters of “0” remains in the FIFO buffers. So it is nec-
essary to reset the FIFO before read enabling the next card after
reading the LCR of the last data.
5) This MCR interface does not read the next card until interrupts are
reset by the main CPU.
(8) VFD Interface
The PSC2 has 2 UARTs (8250) as Mega Macro Function. PSC+80XH
is used as the I/O address for this interface. Only TXD and DTR are out-
putted as UART signals from the PSC2.
UART3: PSC2+(800-807H)
UART4: PSC2+(808-80FH)
(9) Analog Touch Panel Interface
The PSC2 has a UART (8250) as Mega Macro Function. PSC+81XH is
used as the I/O address for this interface. TXD, RXD, DTR, and CTS
are inputted and outputted as UART signals from the PSC2.
UART5: PSC2+(810-817H)
(10) General Purpose I/O Port
A 6-bit I/O port used for general purposes is configured in the PSC.
(11) Mode Key Control and Clerk Key Control (NotUsed)
17-4. PIN ASSIGNMENT
156
155
154
153
152
151
150
148
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
NC
Y737I
GND
Y737O
GND
IS3#
IS4#
KRES1
HTS1
STH1
SCK1
GND
HOP2
HOP1
HIP2
HIP1
HIP0
SW0
SW1
SW2
SW3
SW4
SW5
SW6
SW7
GND
VDD
TXD3
RXD3
DTR3#
DSR3#
RTS3#
CTS3#
DCD3#
RI3#
GND
TXD4
RXD4
DTR4#
DSR4#
RTS4#
DTS4#
DCD4#
RI4#
GND
VDD
TXD2
RXD2
DTR2#
DSR2#
RTS2#
CTS2#
SC
K2
ST
H2
HTS2
KR
ES2
IS53
GND
RI
1#
CTS1#
RTS1#
DSR1#
DTR1#
RX
D1
TX
D
GND
RI
2#
DCD2#
DCD1#
RCP
1
GND
VD
D
RDD1
CLS1
DS
DR3
DR2
DR1
DR0
GND
ST
2
ST
1
ST
0
GND
RI
5#
DCD5#
CTS5#
RTS5#
DSR5#
DTR5#
RX
D5
TXD5
SI
OCS#
RCP
2
RDD2
CLS2
GND
ME
MR#
AE
N
BA
LE
GND
CFSR
MODR
ST
3
GND
SA23
SA22
SA21
SA20
SA19
SA18
SA17
SA16
GND
SA15
SA14
SA13
SA12
SA11
SA10
SA9
GND
SA8
SA7
SA6
SA5
SA4
SA3
SA2
GND
VDD
SA1
SA0
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
GND
IRQ15
IRQ11
IRQ10
IRQ9
IRQ4
IRQ3
REFRESH#
RESETDRV
VDD
GND
MCS16#
IOW#
IOR#
MEMW#
PI
RQ3
PI
RQ4
PI
RQ9
PI
RQ10
PI
RQ11
PI
RQ15
PWRGD
GND
VD
D
PR
AS0
PR
AS1
PR
AS2
PR
AS3
PS
REF
BA
18
GND
BA
8
BA
7
BA
6
BA
5
BA
4
BA
3
BA
2
BA
1
BA
0
VD
D
GND
MROS
#
FROS0#
FROS1#
FROS2#
FROS3#
FROMRP#
F
R
OMWP#
IS6#
GND
TE
ST
1
TE
ST
2
TE
ST
3
TE
ST
4
TE
ST
5
CDV
VF
DOF
F#
FANON
PWRGOOD
PS
CRO
PS
CRI
P
O
FF#
GND
GND
NC
NC
PSC2
LZ9AM22
Содержание UP-5900
Страница 128: ...UP 5900VS PWB LAYOUT 10 1 CHAPTER 10 PWB LAYOUT MAIN PWB UPPER SIDE ...
Страница 129: ...UP 5900VS PWB LAYOUT 10 2 BOTTOM SIDE ...
Страница 130: ...UP 5900VS PWB LAYOUT 10 3 INVERTER PWB UPPER SIDE BOTTOM SIDE UPPER SIDE UPPER SIDE BOTTOM SIDE ...
Страница 131: ...UP 5900VS PWB LAYOUT 10 4 UPPER SIDE BOTTOM SIDE UPPER SIDE BOTTOM SIDE ...