UP-5900VS
CIRCUIT DESCRIPTION
5 – 28
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GENERAL PURPOSE INPUT AND OUTPUT SIGNALS
Some of the General Purpose Input and Output signals are multiplexed with other PIIX4E signals. The usage is determined by the system configura-
tion.
The default pin usage is shown in Table 1 and Table 2. The configuration can be selected via the General Configuration register and X-Bus Chip
Select register.
Table1. GPI Signals
Table2. GPO Signals
Name
Type
Description
GPI[21:0]
I
GENERAL PURPOSE INPUTS. These input signals can be monitored via the GPIREG register located in Function
3 (Power Management) System IO Space at address 30h.
GPO[30:0]
O
GENERAL PURPOSE OUTPUTS. These output signals can be controlled via the GPIREG register located in Func-
tion 3 (Power Management) System IO Space at address 34h.
If a GPO pin is not multiplexed with another signal or defaults to GPO, then its state after reset is the reset condition
of the GPOREG register. If the GPO defaults to another signal, then it defaults to that signal’s state after reset.
The GPO pins that default to GPO remain stable after reset. The others may toggle due to system boot or power
control sequencing after reset prior to their being programmed as GPOs.
The GPO8 signal is driven low upon removal of power from the PIIX4E core power plane. All other GPO signals are
invalid (buffers powered off).
Signal Name
Multiplexed With
Default
Control Register and Bit
(PCI Function 1)
Notes
GPI0
IOCHK#
GPI
GENCFG
Bit 0
Available as GPI only if in EIO bus mode.
GPI1#
GPI
Non-multiplexed GPI which is always available. This signal
when used by power management logic is active low.
GPI[2:4]
REQ[A:C]#
GPI
GENCFG
Bits 8 10
Not available as GPI if used for PC/PCI. Can be individually
enabled, so for instance, GPI[4] is available if REQ[C]# is not
used.
GPI5
APICREQ#
GPI
XBCS
Bit 8
Not available as GPI if using an external APIC.
GPI6
IRQ8#
GPI
GENCFG
Bit 14
Not available as GPI if using external RTC or external APIC.
GPI7
SERIRQ
GPI
GENCFG
Bit 16
Not available as GPI if using Serial IRQ protocol.
GPI8
THRM#
THRM#
GENCFG
Bit 23
Not available as GPI if using thermal monitoring.
GPI9
BATLOW#
BATLOW#
GENCFG
Bit 24
Not available as GPI if using battery low feature.
GPI10
LID#
LID
GENCFG
Bit 25
Not available as GPI if using LID feature.
GPI11
SMBALERT#
SMBALERT#
GENCFG
Bit 15
Not available as GPI if using SMBALERT feature
GPI12
RI#
RI#
GENCFG
Bit 27
Not available if using ring indicator feature
GPI[13:21]
GPI
Non-multiplexed GPIs which are always available.
Signal Name
Multiplexed With
Default
Control Register and Bit
(PCI Function 1)
Notes
GPO0
GPO
Non-multiplexed GPO which is always available.
GPO[1:7]
LA[17:23]
GPO
GENCFG
Bit 0
Available as GPO only if EIO mode.
GPO8
GPO
Non-multiplexed GPO which is always available. The GPO[8]
signal will be driven low upon removal of power from the PIIX4E
core power plane.
GPO[9:11]
GNT[A:C]#
GPO
GENCFG
Bits [8:10]
Not available as GPO if using for PC/PCI. Can be individually
enabled, so GPO[11] is available if REQ[C]# not used.
GPO12
APICACK#
GPO
XBCS
Bit 8
Not available as GPO if using external APIC.
GPO13
APICCS#
GPO
XBCS
Bit 8
Not available as GPO if using external APIC.
GPO14
IRQ0
GPO
XBCS
Bit 8
Not available as GPO if using external APIC.
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