Sharp UP-5900, Руководство по обслуживанию

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UP-5900VS CIRCUIT DESCRIPTION
5 – 40
ID3
ID2
ID1
ID0 99
96
98
100 UART2 Input
Group 1
Identification – These ID signals identify the infrared transceiver for Plug and Play sup-
port. These pins are read after reset.
ID0,1,2 are multiplexed implicitly with IRSL0,1,2 respectively by the UART2 cell.
ID3 is multiplexed with SIN2.
ID2 is multiplexed with BOUT2, DTR2, IRSL2.
ID1 is multiplexed with RTS2, IRSL1
ID0 is multiplexed with SOUT2,IRSL0, IRRX2
INDEX 56 FDC Input
Group 1
Index – This input signal indicates the beginning of an FDD track.
INIT 72 Parallel Port I/O
Group 8
Initialize – When this signal is active low, it causes the printer to be initialized. This sig-
nal is in TRI-STATE after a 1 is loaded into the corresponding control register bit.
An external 4.7 K
Ω
pull-up resistor should be employed.
IOCHRDY 22 ISA-Bus Output
Group 15
I/O Channel Ready – This is the I/O channel ready open drain output signal. When
IOCHRDY is driven low, the EPP extends the host cycle.
IORD 23 ISA-Bus Input
Group 1
I/O Read – An active low RD input signal indicates that the microprocessor has read
data.
IOWR 24 ISA-Bus Input
Group 1
I/O Write – WR is an active low input signal that indicates a write operation from the
microprocessor to the controller.
IRQ1
IRQ7-3
IRQ12 26
31-27
32 ISA-Bus I/O
Group 10
Interrupt Requests 1, 3, 4, 5, 6, 7 and 12 – IRQ polarity and push-pull or open-drain
output selection is software configurable by the logical device mapped to the IRQ line.
Keyboard Controller (KBC) or Mouse interrupts can be configured by the Interrupt
Request Type Select 0 register (index 71h) as either edge or level.
IRRX2,1 100,43 UART2 Input
Group 18
Infrared Reception 1 and 2 – Infrared serial input data.
IRRX1 is multiplexed with P12/DRATE0 and is available only in Two UART mode.
IRRX2 is multiplexed with SOUT2/IRSL0/ID0 and is available only in Full-IR mode.
IRSL0
IRSL1
IRSL2 100
98
96 UART2 Output
Group 12
Infrared Control Signals 0, 1 and 2 – These signals control the Infrared analog front
end. The pins on which these signals are driven is determined by the SuperI/O Config-
uration 2 register (index 22h).
IRSL0 is multiplexed on pin 100 with SOUT2, IRRX2 and ID0, and is available only in
Full-IR mode.
IRSL1 is multiplexed on pin 98 with RTS2 and ID1, and is available only in Full-IR
mode.
IRSL2 is multiplexed on pin 96 with DTR2, BOUT2 and ID2, and is available only in
Full-IR mode.
IRTX 44 UART2 Output
Group 12
Infrared Transmit – Infrared serial output data.
This signal is multiplexed with DENSEL only in Two-UART mode.
KBCLK 59 KBC I/O
Group 6
Keyboard Clock – This I/O pin transfers the keyboard clock between the SuperI/O chip
and the external keyboard using the PS/2 protocol.
This pin is connected internally to the internal TO signal of the KBC.
KBDAT 60 KBC I/O
Group 6
Keyboard Data – This I/O pin transfers the keyboard data between the SuperI/O chip
and the external keyboard using the PS/2 protocol.
This pin is connected internally to KBCfs P10.
MCLK 61 KBC I/O
Group 6
Mouse Clock – This I/O pin transfers the mouse clock between the SuperI/O chip and
the external keyboard using the PS/2 protocol.
This pin is connected internally to KBCfs T1.
MDAT 62 KBC I/O
Group 6
Mouse Data – This I/O pin transfers the mouse data between the SuperI/O chip and the
external keyboard using the PS/2 protocol.
This pin is connected internally to KBCfs P11.
MR 34 ISA-Bus Input
Group 1
Master Reset – An active high MR input signal resets the controller to the idle state,
and resets all disk interface output signals to their inactive states. MR also clears the
DOR, DSR and CCR registers, and resets the MODE command, CONFIGURE com-
mand, and LOCK command parameters to their default values. MR does not affect the
SPECIFY command parameters. MR sets the configuration registers to their selected
default values.
MTR1,0 46,45 FDC Output
Group 11
Motor Select 1,0 – These motor enable lines for drives 0 and 1 are controlled by bits
D7-4 of the Digital Output Register (DOR). They are output signals that are active when
they are low. They are encoded with information to control four FDDs when bit 7 of the
SuperI/O FDC Configuration register is set See DR1,0.
MTR0 is multiplexed with DRATE0 only in Two-UART mode.
MTR1 is multiplexed with P12 only in Two-UART mode.
P12 94, 46 or 43 KBC I/O
Group 7
I/O Port – KBC quasi-bidirectional port for general purpose input and output.
P12 is multiplexed on pin 43 with IRRX1 and DRATE0, on pin 46 with MTR1, and on
pin 94 with DCD2.
P21,P20 64,63 KBC I/O
Group 7
I/O Port – KBC open-drain signals for general purpose input and output. These signals
are controlled by KBC firmware.
Signal/Pin
Name
Pin Number Module
I/O and
Group #
Function