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UP-5900VS

CIRCUIT DESCRIPTION

5 – 8

9-1. PIN ASSIGNMENTS

9-2. PIN DISCRIPTION

A M

V S S

V C C

V S S

D 3 5

D 2 9

D 3 3

D 2 6

D 2 8

D 2 1

D 2 3

D 2 5

V S S

V C C

V S S

D 3 1

V C C

D 4 3

V C C

V S S

D 3 4

D 3 8

V C C

V S S

D 3 9

D 3 6

V C C

D 3 7

D 4 4

V C C

D 3 2

D 2 2

R S V

D 2 7

V S S

D 4 2

D 4 5

D 4 9

V S S

V C C

D 6 3

V R E F 1

V S S

V C C

V S S

V C C

V S S

V C C

V S S

V C C

V S S

V C C

V S S

V C C

V S S

R S V

D 6 2

S L E W

C T R L

R S V

V R E F 0

B P M 1

B P 3

D 4 1

D 5 2

V S S

V C C

V S S

V C C

V S S

V C C

V S S

V C C

V S S

V C C

D 4 0

D 5 9

D 5 5

D 5 4

D 5 8

D 5 0

D 5 6

R S V

B P M 0

C P U P R E S

V C C

V S S

V C C

V S S

V C C

V S S

V C C

V S S

V C C

V S S

V C C

R S V

D 5 1

D 4 7

D 4 8

D 5 7

D 4 6

D 5 3

D 6 0

D 6 1

R S V

P R D Y

V S S

B P 2

R S V

V C C

V S S

V C C

P I C C L K

P I C D 0

P R E Q

V C C

V S S

R S V

P I C D 1

L I N T 1

V C C

V S S

L I N T 0

R S V

V S S

V C C

V S S

R S V

V C C

V S S

V C C

R S V

R T T

C T R L

R S V

V S S

V C C

V S S

P L L 2

R S V

V C C

V S S

V C C

R S V

V C C

V S S

V C C

V S S

V _ 2 . 5

R S V

V C C

V S S

V C C

V _ C M O S

V S S

F E R R

R S V

V C C

V S S

V _ 1 . 5

A 2 0 M

I E R R

F L U S H

V S S

V C C

V S S

INIT

V S S

V C C

V S S

P L L 1

R S V

B C L K

S T P C L K

I G N N E

V S S

D 1 6

D 1 9

D 7

D 3 0

V C C

V R E F 2

D 2 4

D 1 3

D 2 0

V S S

D 1 1

D 3

D 2

D 1 4

V C C

D 1 8

D 9

D 1 2

D 1 0

V S S

R S V

D 1 7

V R E F 3

D 8

D 5

V C C

D 1

D 6

D 4

D 1 5

V S S

R S V

V R E F 4

D 0

R S V

V C C

R S V

R E S E T

R S V

A 2 6

V S S

A 2 9

A 1 8

A 2 7

A 3 0

V C C

A 2 4

A 2 3

R S V

A 2 0

V S S

A 3 1

V R E F 5

A 1 7

A 2 2

V C C

R S V

A 2 5

E D G C T R L

A 1 9

V S S

R S V

A 1 0

A 5

A 8

A 4

B N R

R E Q 1

R E Q 2

R S V

R S 1

V C C

R S 0

T H E R M

T R I P

S L P

V C C

V S S

V C C

A 2 1

V S S

V C C

V S S

V C C

V S S

V C C

V S S

V C C

V S S

V C C

V S S

V C C

V S S

V C C

B S E L 1

B S E L 0

S M I

V I D 3

V C C

V S S

A 2 8

A 3

A 1 1

V R E F 6

A 1 4

R S V

R E Q 0

L O C K

V R E F 7

R S V

P W R G D R S 2

R S V

T M S

V C C

V S S

A 1 5

A 1 3

A 9

R S V

A 7

R E Q 4

R E Q 3

R S V

H I T M

H I T

D B S Y

T H R M D N

T H R M D P

T C K

V I D 0

V I D 2

R S V

V C C

V S S

V C C

V S S

V C C

V S S

V C C

V S S

V C C

V S S

V C C

V S S

V C C

V S S

V C C

V S S

V I D 1

V S S

A 1 2

A 1 6

A 6

R S V

B P R I

D E F E R

R S V

T R D Y

D R D Y

B R 0

A D S

T R S T

T D I

T D O

P I N S I D E V I E W

24 25

31 32

24 25

31 32

A M

Signal

Type

Description

A[31:3]#

I/O

The A[31:3]# (Address) signals define a 2

-byte physical memory address space.

When ADS# is active, these pins transmit the address of a transaction; when ADS# is inactive, these pins transmit
transaction type information. These signals must connect the appropriate pins of all agents on the Intel Celeron pro-
cessor system bus. The A[31:24]# signals are parity-protected by the AP1# parity signal, and the A[23:3]# signals are
parity-protected by the AP0# parity signal.
On the active-to-inactive transition of RESET#, the processors sample the A[31:3]# pins to determine their power-on
configuration.

A20M#

If the A20M# (Address-20 Mask) input signal is asserted, the Intel Celeron processor masks physical address bit 20
(A20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. Asserting
A20M# emulates the 8086 processor’s address wrap-around at the 1MB boundary.
Assertion of A20M# is only supported in real mode.
A20M# is an asynchronous signal. However, to ensure recognition of this signal following an I/O write instruction, it
must be valid along with the TRDY# assertion of the corresponding I/O Write bus transaction.

ADS#

I/O

The ADS# (Address Strobe) signal is asserted to indicate the validity of the transaction address on the A[31:3]# pins.
All bus agents observe the ADS# activation to begin parity checking, protocol checking, address decode, internal
snoop, or deferred reply ID match operations associated with the new transaction.
This signal must connect the appropriate pins on all Intel Celeron processor system bus agents.

BCLK

The BCLK (Bus Clock) signal determines the bus frequency. All Intel Celeron processor system bus agents must
receive this signal to drive their outputs and latch their inputs on the BCLK rising edge.
All external timing parameters are specified with respect to the BCLK signal.

BNR#

I/O

The BNR# (Block Next Request) signal is used to assert a bus stall by any bus agent who is unable to accept new bus
transactions. During a bus stall, the current bus owner cannot issue any new transactions.
Since multiple agents might need to request a bus stall at the same time, BNR# is a wire-OR signal which must con-
nect the appropriate pins of all Intel Celeron processor system bus agents. In order to avoid wire-OR glitches associ-
ated with simultaneous edge transitions driven by multiple drivers, BNR# is activated on specific clock edges and
sampled on specific clock edges.

BP[3:2]#

I/O

The BP[3:2]# (Breakpoint) signals are outputs from the processor that indicate the status of breakpoints.

BPM[1:0]#

I/O

The BPM[1:0]# (Breakpoint Monitor) signals are breakpoint and performance monitor signals. They are outputs from
the processor which indicate the status of breakpoints and programmable counters used for monitoring processor per-
formance.

BPRI#

The BPRI# (Bus Priority Request) signal is used to arbitrate for ownership of the Intel Celeron processor system bus. It
must connect the appropriate pins of all Intel Celeron processor system bus agents. Observing BPRI# active (as
asserted by the priority agent) causes all other agents to stop issuing new requests, unless such requests are part of
an ongoing locked operation. The priority agent keeps BPRI# asserted until all of its requests are completed, then
releases the bus by deasserting BPRI#.