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Section 14 Direct Memory Access Controller (DMAC)
SH7751 Group, SH7751R Group
Page 504 of 1128
R01UH0457EJ0301 Rev. 3.01
Sep 24, 2013
14.2
Register Descriptions
14.2.1
DMA Source Address Registers 0–3 (SAR0–SAR3)
Bit:
31 30 29 28 27 26 25 24
Initial
value:
— — — — — — — —
R/W:
R/W R/W R/W R/W R/W R/W R/W R/W
Bit:
23
0
· · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · ·
Initial value:
—
· · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · ·
—
R/W:
R/W
· · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · ·
R/W
DMA source address registers 0–3 (SAR0–SAR3) are 32-bit readable/writable registers that
specify the source address of a DMA transfer. These registers have a counter feedback function,
and during a DMA transfer they indicate the next source address. In single address mode, the SAR
value is ignored when a device with DACK has been specified as the transfer source.
Specify a 16-bit, 32-bit, 64-bit, or 32-byte boundary address when performing a 16-bit, 32-bit, 64-
bit, or 32-byte data transfer, respectively. If a different address is specified, an address error will
be detected and the DMAC will halt.
The initial value of these registers after a power-on or manual reset is undefined. They retain their
values in standby mode, sleep mode, and deep sleep mode.
Содержание SH7751 Group
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Страница 190: ...Section 4 Caches SH7751 Group SH7751R Group Page 136 of 1128 R01UH0457EJ0301 Rev 3 01 Sep 24 2013 ...
Страница 226: ...Section 5 Exceptions SH7751 Group SH7751R Group Page 172 of 1128 R01UH0457EJ0301 Rev 3 01 Sep 24 2013 ...
Страница 264: ...Section 7 Instruction Set SH7751 Group SH7751R Group Page 210 of 1128 R01UH0457EJ0301 Rev 3 01 Sep 24 2013 ...
Страница 320: ...Section 9 Power Down Modes SH7751 Group SH7751R Group Page 266 of 1128 R01UH0457EJ0301 Rev 3 01 Sep 24 2013 ...
Страница 344: ...Section 10 Clock Oscillation Circuits SH7751 Group SH7751R Group Page 290 of 1128 R01UH0457EJ0301 Rev 3 01 Sep 24 2013 ...
Страница 388: ...Section 12 Timer Unit TMU SH7751 Group SH7751R Group Page 334 of 1128 R01UH0457EJ0301 Rev 3 01 Sep 24 2013 ...
Страница 800: ...Section 17 Smart Card Interface SH7751 Group SH7751R Group Page 746 of 1128 R01UH0457EJ0301 Rev 3 01 Sep 24 2013 ...
Страница 848: ...Section 19 Interrupt Controller INTC SH7751 Group SH7751R Group Page 794 of 1128 R01UH0457EJ0301 Rev 3 01 Sep 24 2013 ...
Страница 876: ...Section 20 User Break Controller UBC SH7751 Group SH7751R Group Page 822 of 1128 R01UH0457EJ0301 Rev 3 01 Sep 24 2013 ...
Страница 1036: ...Section 22 PCI Controller PCIC SH7751 Group SH7751R Group Page 982 of 1128 R01UH0457EJ0301 Rev 3 01 Sep 24 2013 ...
Страница 1152: ...Appendix C Mode Pin Settings SH7751 Group SH7751R Group Page 1098 of 1128 R01UH0457EJ0301 Rev 3 01 Sep 24 2013 ...
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