Section 2
CPU
Rev. 1.00 Apr. 28, 2008 Page 33 of 994
REJ09B0452-0100
H'0000
H'0001
H'0002
H'0003
H'0004
H'0005
H'0006
H'0007
H'0008
H'0009
H'000A
H'000B
Exception vector 1
Exception vector 2
Exception vector 3
Exception vector 5
Exception vector 6
Exception
vector table
Exception vector 4
Figure 2.1 Exception Vector Table (Normal Mode)
PC
(16 bits)
EXR
*
1
Reserved
*
1
,
*
3
CCR
CCR
*
3
PC
(16 bits)
SP
SP
(SP
*
2
1. When EXR is not used it is not stored on the stack.
2. SP when EXR is not used.
3. lgnored when returning.
Notes:
(b) Exception Handling
(a) Subroutine Branch
)
Figure 2.2 Stack Structure in Normal Mode
Содержание H8S/2100 Series
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Страница 92: ...Section 2 CPU Rev 1 00 Apr 28 2008 Page 66 of 994 REJ09B0452 0100...
Страница 158: ...Section 5 Interrupt Controller Rev 1 00 Apr 28 2008 Page 132 of 994 REJ09B0452 0100...
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Страница 330: ...Section 10 16 Bit Timer Pulse Unit TPU Rev 1 00 Apr 28 2008 Page 304 of 994 REJ09B0452 0100...
Страница 354: ...Section 11 16 Bit Cycle Measurement Timer TCM Rev 1 00 Apr 28 2008 Page 328 of 994 REJ09B0452 0100...
Страница 380: ...Section 12 16 Bit Duty Period Measurement Timer TDP Rev 1 00 Apr 28 2008 Page 354 of 994 REJ09B0452 0100...
Страница 416: ...Section 13 8 Bit Timer TMR Rev 1 00 Apr 28 2008 Page 390 of 994 REJ09B0452 0100...
Страница 494: ...Section 15 Serial Communication Interface SCI Rev 1 00 Apr 28 2008 Page 468 of 994 REJ09B0452 0100...
Страница 612: ...Section 18 I 2 C Bus Interface IIC Rev 1 00 Apr 28 2008 Page 586 of 994 REJ09B0452 0100...
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