Renesas H8S/2100 Series, Руководство по оборудованию

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Section 20 LPC Interface (LPC)
Rev. 1.00 Apr. 28, 2008 Page 661 of 994
REJ09B0452-0100
20.4.2 LPC I/O Cycles
There are 12 types of LPC transfer cycle: LPC memory read, LPC memory write, I/O read, I/O
write, DMA read, DMA write, bus master memory read, bus master memory write, bus master I/O
read, bus master I/O write, FW memory read, and FW memory write. Of these, the LPC of this
LSI supports I/O read and I/O write.
An LPC transfer cycle is started when the
LFRAME
signal goes low in the bus idle state. If the
LFRAME
signal goes low when the bus is not idle, this means that a forced termination (abort) of
the LPC transfer cycle has been requested.
In an I/O read cycle or I/O write cycle, transfer is carried out using LAD3 to LAD0 in the
following order, in synchronization with LCLK. The host can be made to wait by sending back a
value other than B'0000 in the slave's synchronization return cycle, but with the LPC of this LSI a
value of B'0000 always returns.
If the received address matches the host address in an LPC register (IDR, ODR, STR, and TWR),
the LPC interface enters the busy state; it returns to the idle state by output of a state count 12
turnaround. Register and flag changes are made at this timing, so in the event of a transfer cycle
forced termination (abort), registers and flags are not changed.
The timing of the
LFRAME
, LCLK, and LAD signals is shown in figures 20.2 and 20.3.