Renesas H8S/2100 Series, Руководство по оборудованию

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Section 28 Electrical Characteristics
Rev. 1.00 Apr. 28, 2008 Page 968 of 994
REJ09B0452-0100
28.3.3 Timing of On-Chip Peripheral Modules
Table 28.7 shows the on-chip peripheral module timing. The on-chip peripheral modules that can
be operated by the subclock (
φ
= 32.768 kHz) are I/O ports, external interrupts (NMI, IRQ0 to
IRQ15, KIN0 to KIN15, WUE8 to WUE15, and KBCA to KBCD) and watchdog timer (WDT_1)
only. The system clock or LCLK operation can be used in the FSI.
Table 28.7 Timing of On-Chip Peripheral Modules
Conditions: V
CC
= 3.0 V to 3.6 V, V
SS
= 0 V,
φ
= 32.768 kHz*
1
,
φ
= 8 MHz to maximum
operating frequency, FSICK = 8 MHz to maximum operating frequency or LCLK
(33 MHz)
Item Symbol Min. Max. Unit
Test
Conditions
Output data delay time
*
2
t
PWD

50
Input data setup time t
PRS
30

I/O ports
Input data hold time t
PRH
30

ns Figure 28.9
Timer output delay time t
TOCD

50
Timer input setup time t
TICS
30

Figure 28.10
Timer clock input setup time t
TCKS
30

ns
Single edge t
TCKWH
1.5

TPU
Timer clock
pulse width
Both edges t
TCKWL
2.5

t
cyc
Figure 28.11
Timer output delay time t
TMOD

50 Figure 28.12
Timer reset input setup time t
TMRS
30

Figure 28.14
Timer clock input setup time t
TMCS
30

ns
Single edge t
TMCWH
1.5

TMR
Timer clock
pulse width
Both edges t
TMCWL
2.5

t
cyc
Figure 28.13
TCM input setup time t
TCMS
30

Figure 28.15
TCM clock input setup time t
TCMCKS
30

ns TCM
TCM clock pulse width t
TCMCKW
1.5

t
cyc
Figure 28.16
TDP input setup time t
TDPS
30

Figure 28.17
TDP clock input setup time t
TDPCKS
30

ns TDP
TDP clock pulse width t
TDPCKW
1.5

t
cyc
Figure 28.18
PWMU, PWMX Pulse output delay time t
PWOD

50 ns Figure 28.19
Asynchronous t
Scyc
4

Input clock cycle
Synchronous 6

t
cyc
SCI
Input clock pulse width t
SCKW
0.4 0.6 t
Scyc
Figure 28.20